Searched full:sel (Results 1 – 25 of 59) sorted by relevance
123
| /Documentation/userspace-api/media/v4l/ |
| D | selection-api-examples.rst | 16 struct v4l2_selection sel = {
20 ret = ioctl(fd, VIDIOC_G_SELECTION, &sel);
23 sel.target = V4L2_SEL_TGT_CROP;
24 ret = ioctl(fd, VIDIOC_S_SELECTION, &sel);
36 struct v4l2_selection sel = {
42 ret = ioctl(fd, VIDIOC_G_SELECTION, &sel);
46 r.width = sel.r.width / 2;
47 r.height = sel.r.height / 2;
48 r.left = sel.r.width / 4;
49 r.top = sel.r.height / 4;
[all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | ti,phy-gmii-sel.yaml | 5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
51 - ti,am3352-phy-gmii-sel
52 - ti,dra7xx-phy-gmii-sel
53 - ti,am43xx-phy-gmii-sel
54 - ti,dm814-phy-gmii-sel
55 - ti,am654-phy-gmii-sel
56 - ti,j7200-cpsw5g-phy-gmii-sel
57 - ti,j721e-cpsw9g-phy-gmii-sel
58 - ti,j784s4-cpsw9g-phy-gmii-sel
86 - ti,dra7xx-phy-gmii-sel
[all …]
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| D | qcom,sc8280xp-qmp-pcie-phy.yaml | 83 qcom,4ln-config-sel:
130 - qcom,4ln-config-sel
287 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
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| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-am654.yaml | 61 ti,otap-del-sel-legacy:
67 ti,otap-del-sel-mmc-hs:
73 ti,otap-del-sel-sd-hs:
79 ti,otap-del-sel-sdr12:
85 ti,otap-del-sel-sdr25:
91 ti,otap-del-sel-sdr50:
97 ti,otap-del-sel-sdr104:
103 ti,otap-del-sel-ddr50:
109 ti,otap-del-sel-ddr52:
115 ti,otap-del-sel-hs200:
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| /Documentation/devicetree/bindings/net/ |
| D | cpsw-phy-sel.txt | 5 - compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and
6 "ti,dra7xx-cpsw-phy-sel" for dra7xx platform
7 "ti,am43xx-cpsw-phy-sel" for am43xx platform
18 phy_sel: cpsw-phy-sel@44e10650 {
19 compatible = "ti,am3352-cpsw-phy-sel";
21 reg-names = "gmii-sel";
25 phy_sel: cpsw-phy-sel@44e10650 {
26 compatible = "ti,am3352-cpsw-phy-sel";
28 reg-names = "gmii-sel";
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| D | cpsw.txt | 22 - cpsw-phy-sel : Specifies the phandle to the CPSW phy mode selection
23 device. See also cpsw-phy-sel.txt for its binding.
24 Note that in legacy cases cpsw-phy-sel may be
48 - phys : phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt)
86 cpsw-phy-sel = <&phy_sel>;
117 cpsw-phy-sel = <&phy_sel>;
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| D | ti,dp83869.yaml | 56 ti,clk-output-sel:
96 ti,clk-output-sel = <DP83869_CLK_O_SEL_CHN_A_RCLK>;
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| D | ti,dp83867.yaml | 71 ti,clk-output-sel:
137 ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
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| /Documentation/devicetree/bindings/clock/ |
| D | renesas,rcar-usb2-clock-sel.yaml | 4 $id: http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#
38 - renesas,r8a774a1-rcar-usb2-clock-sel # RZ/G2M
39 - renesas,r8a774b1-rcar-usb2-clock-sel # RZ/G2N
40 - renesas,r8a774e1-rcar-usb2-clock-sel # RZ/G2H
41 - renesas,r8a7795-rcar-usb2-clock-sel # R-Car H3
42 - renesas,r8a7796-rcar-usb2-clock-sel # R-Car M3-W
43 - renesas,r8a77961-rcar-usb2-clock-sel # R-Car M3-W+
44 - const: renesas,rcar-gen3-usb2-clock-sel
91 compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
92 "renesas,rcar-gen3-usb2-clock-sel";
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| /Documentation/devicetree/bindings/sound/ |
| D | da7218.txt | 32 - dlg,mic1-amp-in-sel : Mic1 input source type
34 - dlg,mic2-amp-in-sel : Mic2 input source type
36 - dlg,dmic1-data-sel : DMIC1 channel select based on clock edge.
42 - dlg,dmic2-data-sel : DMic2 channel select based on clock edge.
86 dlg,mic1-amp-in-sel = "diff";
87 dlg,mic2-amp-in-sel = "diff";
89 dlg,dmic1-data-sel = "lrise_rfall";
92 dlg,dmic2-data-sel = "lrise_rfall";
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| D | mt2701-cs42448.txt | 11 - i2s1-in-sel-gpio1, i2s1-in-sel-gpio2: Should specify two gpio pins to
41 i2s1-in-sel-gpio1 = <&pio 53 0>;
42 i2s1-in-sel-gpio2 = <&pio 54 0>;
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| D | samsung,midas-audio.yaml | 59 fm-sel-gpios:
63 lineout-sel-gpios:
115 fm-sel-gpios = <&gpaa0 3 GPIO_ACTIVE_HIGH>;
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| D | mediatek,mt7986-afe.yaml | 47 - const: sel
102 - const: sel
127 - const: sel
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| D | samsung,aries-wm8994.yaml | 70 earpath-sel-gpios:
97 - earpath-sel-gpios
117 earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>;
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| D | dlg,da7213.yaml | 43 dlg,dmic-data-sel:
99 dlg,dmic-data-sel = "lrise_rfall";
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-cbus-gpio.txt | 5 - gpios: clk, dat, sel
18 &gpio 64 0 /* sel */
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| /Documentation/devicetree/bindings/mfd/ |
| D | rohm,bd9576-pmic.yaml | 47 rohm,ddr-sel-low:
50 the ddr-sel pin low or high. Set this property if ddr-sel is grounded.
97 rohm,ddr-sel-low;
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lm3532.txt | 36 - ti,als1-imp-sel - ALS1 impedance resistor selection in Ohms
37 - ti,als2-imp-sel - ALS2 impedance resistor selection in Ohms
82 ti,als1-imp-sel = <4110>;
83 ti,als2-imp-sel = <2180>;
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| D | leds-lp55xx.yaml | 54 pwr-sel:
163 pwr-sel: false
186 pwr-sel = /bits/ 8 <3>; /* D1~9 connected to VOUT */
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| /Documentation/devicetree/bindings/input/ |
| D | ti,drv260x.yaml | 43 library-sel:
86 - library-sel
105 library-sel = <DRV260X_LIB_LRA>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx7d-pinctrl.yaml | 26 fsl,input-sel:
86 - fsl,input-sel
106 fsl,input-sel = <&iomuxc>;
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| /Documentation/devicetree/bindings/iio/chemical/ |
| D | sensirion,scd30.yaml | 29 sensirion,sel-gpios:
30 description: GPIO connected to the SEL line
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-fsl-lpspi.yaml | 55 fsl,spi-only-use-cs1-sel:
95 fsl,spi-only-use-cs1-sel;
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| D | mediatek,spi-mt65xx.yaml | 70 - const: sel-clk
111 clock-names = "parent-clk", "sel-clk", "spi-clk";
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| /Documentation/devicetree/bindings/media/ |
| D | mediatek,vcodec-subdev-decoder.yaml | 175 - const: sel
191 - const: sel
236 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
262 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
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