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/Documentation/devicetree/bindings/clock/ti/davinci/
Dda8xx-cfgchip.txt13 - compatible: shall be "ti,da830-usb-phy-clocks".
14 - #clock-cells: from common clock binding; shall be set to 1.
16 - clock-names: shall be "fck", "usb_refclkin", "auxclk"
24 - compatible: shall be "ti,da830-tbclksync".
25 - #clock-cells: from common clock binding; shall be set to 0.
27 - clock-names: shall be "fck"
32 - compatible: shall be "ti,da830-div4p5ena".
33 - #clock-cells: from common clock binding; shall be set to 0.
35 - clock-names: shall be "pll0_pllout"
40 - compatible: shall be "ti,da850-async1-clksrc".
[all …]
Dpll.txt8 - compatible: shall be one of:
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15 - for "ti,da850-pll1", shall be "clksrc"
30 - #clock-cells: shall be 0
38 - #clock-cells: shall be 1
45 - #clock-cells: shall be 0
51 - #clock-cells: shall be 0
Dpsc.txt7 - compatible: shall be one of:
11 - #clock-cells: from common clock binding; shall be set to 1
12 - #power-domain-cells: from generic power domain binding; shall be set to 1.
15 - for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
17 - for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
20 - #reset-cells: from reset binding; shall be set to 1 - only applicable when
25 Clock, power domain and reset consumers shall use the local power domain
/Documentation/devicetree/bindings/interrupt-controller/
Dopen-pic.txt14 shall be <string> and the value shall include "open-pic".
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
20 as an Open PIC. No property value shall be defined.
23 interrupt source. The type shall be a <u32> and the value shall be 2.
26 address. The type shall be <u32> and the value shall be 0. As such,
32 shall not be reset during runtime initialization. No property value shall
34 initialization related to interrupt sources shall be limited to sources
74 // The PIC shall not be reset.
Dimg,pdc-intc.txt11 The type shall be <string> and the value shall include "img,pdc-intc".
14 addressable register space. The type shall be <prop-encoded-array>.
17 as an interrupt controller. No property value shall be defined.
20 interrupt source. The type shall be a <u32> and the value shall be 2.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral
Dmarvell,orion-intc.txt6 - compatible: shall be "marvell,orion-intc"
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
29 - compatible: shall be "marvell,orion-bridge-intc"
33 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
/Documentation/devicetree/bindings/clock/
Dxgene.txt8 - compatible : shall be one of the following:
17 - reg : shall be the physical PLL register address for the pll clock.
18 - clocks : shall be the input parent clock phandle for the clock. This should
20 - #clock-cells : shall be set to 1.
21 - clock-output-names : shall be the name of the PLL referenced by derive
24 - clock-names : shall be the name of the PLL. If missing, use the device name.
27 - reg : shall be the physical register address for the pmd clock.
28 - clocks : shall be the input parent clock phandle for the clock.
29 - #clock-cells : shall be set to 1.
30 - clock-output-names : shall be the name of the clock referenced by derive
[all …]
Dvt8500.txt8 - compatible : shall be one of the following:
16 - reg : shall be the control register offset from PMC base for the pll clock.
17 - clocks : shall be the input parent clock phandle for the clock. This should
19 - #clock-cells : from common clock binding; shall be set to 0.
22 - clocks : shall be the input parent clock phandle for the clock. This should
24 - #clock-cells : from common clock binding; shall be set to 0.
36 - enable-reg : shall be the register offset from PMC base for the enable
38 - enable-bit : shall be the bit within enable-reg to enable/disable the clock.
44 - divisor-reg : shall be the register offset from PMC base for the divisor
47 - divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
Dti,cdce706.txt7 - compatible: shall be "ti,cdce706".
8 - reg: i2c device address, shall be in range [0x68...0x6b].
9 - #clock-cells: from common clock binding; shall be set to 1.
11 handles, shall be reference clock(s) connected to CLK_IN0
13 - clock-names: shall be clk_in0 and/or clk_in1. Use clk_in0
Dmicrochip,pic32.txt10 - compatible: shall be "microchip,pic32mzda-clk".
11 - reg: shall contain base address and length of clock registers.
12 - #clock-cells: shall be 1.
15 - microchip,pic32mzda-sosc: shall be added only if platform has
28 The clock consumer shall specify the desired clock-output of the clock
Dkeystone-pll.txt12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
41 - #clock-cells : from common clock binding; shall be set to 0.
42 - compatible : shall be "ti,keystone,pll-mux-clock"
63 - #clock-cells : from common clock binding; shall be set to 0.
64 - compatible : shall be "ti,keystone,pll-divider-clock"
Daltr_socfpga.txt8 - compatible : shall be one of the following:
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
Ddove-divider-clock.txt17 - compatible : shall be "marvell,dove-divider-clock"
18 - reg : shall be the register address of the Core PLL and Clock Divider
22 - #clock-cells : from common clock binding; shall be set to 1
Dlsi,axm5516-clks.txt5 - compatible : shall contain "lsi,axm5516-clks"
6 - reg : shall contain base register location and length
7 - #clock-cells : shall contain 1
/Documentation/devicetree/bindings/perf/
Dapm-xgene-pmu.txt14 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
19 - reg : First resource shall be the CPU bus PMU resource.
23 - compatible : Shall be "apm,xgene-pmu-l3c".
24 - reg : First resource shall be the L3C PMU resource.
27 - compatible : Shall be "apm,xgene-pmu-iob".
28 - reg : First resource shall be the IOB PMU resource.
31 - compatible : Shall be "apm,xgene-pmu-mcb".
32 - reg : First resource shall be the MCB PMU resource.
36 - compatible : Shall be "apm,xgene-pmu-mc".
37 - reg : First resource shall be the MC PMU resource.
/Documentation/devicetree/bindings/edac/
Dapm-xgene-edac.txt14 - compatible : Shall be "apm,xgene-edac".
23 - reg : First resource shall be the CPU bus (PCP) resource.
28 - compatible : Shall be "apm,xgene-edac-mc".
29 - reg : First resource shall be the memory controller unit
34 - compatible : Shall be "apm,xgene-edac-pmd" or
36 - reg : First resource shall be the PMD resource.
40 - compatible : Shall be "apm,xgene-edac-l3" or
42 - reg : First resource shall be the L3 EDAC resource.
45 - compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or
48 - reg : First resource shall be the SoC EDAC resource.
/Documentation/gpu/
Ddrm-usage-stats.rst22 - File shall contain one key value pair per one line of text.
24 - All keys shall be prefixed with `drm-`.
25 - Whitespace between the delimiter and first non-whitespace character shall be
50 String shall contain the name this driver registered as via the respective
70 Uniqueness of the value shall be either globally unique, or unique within the
71 scope of each device, in which case `drm-pdev` shall be present as well.
81 GPUs usually contain multiple execution engines. Each shall be given a stable
85 Value shall be in specified time units which the respective GPU engine spent
97 drm-engine-<keystr> tag and shall contain a greater than zero number in case the
100 In the absence of this tag parser shall assume capacity of one. Zero capacity
[all …]
/Documentation/devicetree/bindings/ata/
Dapm-xgene.txt7 - compatible : Shall contain:
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
13 Third memory resource shall be the host controller
15 4th memory resource shall be the host controller
17 5th optional memory resource shall be the host
28 - status : Shall be "ok" if enabled or "disabled" if disabled.
/Documentation/devicetree/bindings/power/
Dti-smartreflex.txt8 compatible: Shall be one of the following:
15 reg: Shall contain the device instance IO range
17 interrupts: Shall contain the device instance interrupt
22 ti,hwmods: Shall contain the TI interconnect module name if needed
/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic-msgr.txt10 block. The type shall be <string-list> and the value shall be of the form
15 message register block's addressable register space. The type shall be
20 cell is interrupt-number and second cell is level-sense. The type shall be
28 Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall
38 Numbers shall start at 0.
/Documentation/devicetree/bindings/arm/marvell/
Darmada-370-xp.txt5 shall have the following property:
11 In addition, boards using the Marvell Armada 370 SoC shall have the
18 In addition, boards using the Marvell Armada XP SoC shall have the
D98dx3236.txt5 shall have the following property:
11 In addition, boards using the Marvell 98DX3336 SoC shall have the
18 In addition, boards using the Marvell 98DX4251 SoC shall have the
Darmada-39x.txt4 Boards with a SoC of the Marvell Armada 39x family shall have the
11 In addition, boards using the Marvell Armada 395 SoC shall have the
22 Boards using the Marvell Armada 398 SoC shall have the following
/Documentation/firmware-guide/acpi/dsd/
Ddata-node-references.rst20 The hierarchical data extension node which is referred to shall be located
24 The keys in the hierarchical data nodes shall consist of the name of the node,
26 or postfixes). The same ACPI object shall include the _DSD property extension
27 with a property "reg" that shall have the same numerical value as the number of
31 "reg" property shall be omitted from the ACPI object's _DSD properties and the
32 "@" character and the number shall be omitted from the hierarchical data
/Documentation/devicetree/bindings/clock/ti/
Dcomposite.txt14 The binding must provide a list of the component clocks that shall be
15 merged to this clock. The component clocks shall be of one of the
24 - compatible : shall be: "ti,composite-clock"
26 - #clock-cells : from common clock binding; shall be set to 0.

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