Home
last modified time | relevance | path

Searched +full:shared +full:- +full:interrupt (Results 1 – 25 of 209) sorted by relevance

123456789

/Documentation/devicetree/bindings/mailbox/
Dnvidia,tegra186-hsp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 The features that HSP supported are shared mailboxes, shared
29 For shared mailboxes, the first cell composed of two fields:
30 - bits 15..8:
31 A bit mask of flags that further specifies the type of shared
[all …]
Darm,mhuv3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Cristian Marussi <cristian.marussi@arm.com>
27 - Configure the MHU
28 - Send Transfers to the Receiver
29 - Optionally receive acknowledgment of a Transfer from the Receiver
32 - Configure the MHU
33 - Receive Transfers from the Sender
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dfsl,ls-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This interrupt controller hardware is a second level interrupt controller that
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
19 - Frank Li <Frank.Li@nxp.com>
24 - fsl,ls1012a-msi
[all …]
Dst,spear3xx-shirq.txt1 * SPEAr Shared IRQ layer (shirq)
3 SPEAr3xx architecture includes shared/multiplexed irqs for certain set
4 of devices. The multiplexor provides a single interrupt to parent
5 interrupt controller (VIC) on behalf of a group of devices.
13 A single node in the device tree is used to describe the shared
14 interrupt multiplexor (one node for all groups). A group in the
15 interrupt controller shares config/control registers with other groups.
16 For example, a 32-bit interrupt enable/disable config register can
17 accommodate up to 4 interrupt groups.
20 - compatible: should be, either of
[all …]
Dmarvell,icu.txt1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
[all …]
Dti,pruss-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI PRU-ICSS Local Interrupt Controller
10 - Suman Anna <s-anna@ti.com>
13 Each PRU-ICSS has a single interrupt controller instance that is common
14 to all the PRU cores. Most interrupt controllers can route 64 input events
19 remaining 8 (2 through 9) connected to external interrupt controllers
22 The property "ti,irqs-reserved" is used for denoting the connection
[all …]
/Documentation/devicetree/bindings/net/
Dcavium-mix.txt4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
11 AGL registers. The third bank are the AGL registers shared by all
12 MIX devices present. The fourth bank is the AGL_PRT_CTL shared by
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
19 interrupt routing and the second the routing for the AGL interrupts.
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
[all …]
/Documentation/devicetree/bindings/gpio/
Dsprd,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
16 The controller's registers are organized as sets of sixteen 16-bit
18 interrupt is shared for all of the banks handled by the controller.
23 - const: sprd,sc9860-gpio
24 - items:
[all …]
Dfsl-imx-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
17 - enum:
18 - fsl,imx1-gpio
19 - fsl,imx21-gpio
[all …]
Dbrcm,brcmstb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The controller's registers are organized as sets of eight 32-bit
12 interrupt is shared for all of the banks handled by the controller.
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
[all …]
/Documentation/devicetree/bindings/display/ti/
Dti,j721e-dss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
22 const: ti,j721e-dss
26 - description: common_m DSS Master common
27 - description: common_s0 DSS Shared common 0
28 - description: common_s1 DSS Shared common 1
[all …]
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,smsm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory State Machine
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The Shared Memory State Machine facilitates broadcasting of single bit state
25 '#address-cells':
28 qcom,local-host:
[all …]
Dqcom,smp2p.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory Point 2 Point
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The Shared Memory Point to Point (SMP2P) protocol facilitates communication
16 of a single 32-bit value between two processors. Each value has a single
35 $ref: /schemas/types.yaml#/definitions/phandle-array
[all …]
Dqcom,smd.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory Driver
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The Qualcomm Shared Memory Driver is a FIFO based communication channel for
18 Using the top-level SMD node is deprecated. Instead, the SMD edges are defined
29 "^smd-edge|rpm$":
[all …]
/Documentation/virt/hyperv/
Dclocks.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----
8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
14 per-CPU timers as described in the TLFS, they are not used by the
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead.
[all …]
/Documentation/devicetree/bindings/perf/
Darm,dsu-pmu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
11 - Suzuki K Poulose <suzuki.poulose@arm.com>
12 - Robin Murphy <robin.murphy@arm.com>
15 ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
18 DSU. The PMU provides independent 32-bit counters that can count any of the
19 supported events, along with a 64-bit cycle counter. The PMU is accessed via
[all …]
/Documentation/power/
Dsuspend-and-interrupts.rst10 -----------------------------------
12 Device interrupt request lines (IRQs) are generally disabled during system
14 ->prepare, ->suspend and ->suspend_late callbacks have been executed for all
21 interrupt handlers for shared IRQs that device drivers implementing them were
29 Device IRQs are re-enabled during system resume, right before the "early" phase
30 of resuming devices (that is, before starting to execute ->resume_early
35 ------------------------
38 suspend-resume cycle, including the "noirq" phases of suspending and resuming
41 but also to IPIs and to some other special-purpose interrupts.
44 requesting a special-purpose interrupt. It causes suspend_device_irqs() to
[all …]
/Documentation/devicetree/bindings/arm/
Datmel-sysregs.txt4 - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
5 - reg : Should contain registers location and length
8 - compatible: Should be "atmel,at91sam9260-pit"
9 - reg: Should contain registers location and length
10 - interrupts: Should contain interrupt for the PIT which is the IRQ line
11 shared across all System Controller members.
14 - compatible: Should be "microchip,sam9x60-pit64b" or
15 "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
16 - reg: Should contain registers location and length
17 - interrupts: Should contain interrupt for PIT64B timer
[all …]
/Documentation/devicetree/bindings/sound/
Dsprd-mcdt.txt1 Spreadtrum Multi-Channel Data Transfer Binding
3 The Multi-channel data transfer controller is used for sound stream
6 configured with DMA mode or interrupt mode.
9 - compatible: Should be "sprd,sc9860-mcdt".
10 - reg: Should contain registers address and length.
11 - interrupts: Should contain one interrupt shared by all channel.
16 compatible = "sprd,sc9860-mcdt";
/Documentation/devicetree/bindings/display/
Darm,malidp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Mali Display Processor (Mali-DP)
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
22 - arm,mali-dp500
23 - arm,mali-dp550
24 - arm,mali-dp650
31 - description:
[all …]
/Documentation/locking/
Dspinlocks.rst20 there is only one thread-of-control within the region(s) protected by that
26 Documentation/memory-barriers.txt
33 spinlock for most things - using more than one spinlock can make things a
41 shared data structures **everywhere** they are used. The spinlocks are most
45 NOTE! The spin-lock is safe only when you **also** use the lock itself
47 touches a shared variable has to agree about the spinlock they want
50 ----
52 Lesson 2: reader-writer spinlocks.
56 to mostly read from the shared variables, the reader-writer locks
61 NOTE! reader-writer locks require more atomic memory operations than
[all …]
/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
20 communication, and an interrupt controller.
[all …]
/Documentation/devicetree/bindings/bus/
Dfsl,spba-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Shared Peripherals Bus Interface
10 - Shawn Guo <shawnguo@kernel.org>
13 A simple bus enabling access to shared peripherals.
15 The "spba-bus" follows the "simple-bus" set of properties, as
17 "simple-bus" because the SDMA controller uses this compatible flag to
20 the SDMA controller itself has its interrupt and clock assignments.
[all …]
Dmoxtet.txt4 - compatible : Should be "cznic,moxtet"
5 - #address-cells : Has to be 1
6 - #size-cells : Has to be 0
7 - spi-cpol : Required inverted clock polarity
8 - spi-cpha : Required shifted clock phase
9 - interrupts : Must contain reference to the shared interrupt line
10 - interrupt-controller : Required
11 - #interrupt-cells : Has to be 1
14 ../spi/spi-bus.txt.
17 - reg : Should be position on the Moxtet bus (how many Moxtet
[all …]
/Documentation/devicetree/bindings/dma/
Dbrcm,bcm2835-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/brcm,bcm2835-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Saenz Julienne <nsaenz@kernel.org>
19 - $ref: dma-controller.yaml#
23 const: brcm,bcm2835-dma
35 interrupt-names:
39 '#dma-cells':
43 brcm,dma-channel-mask:
[all …]

123456789