Searched +full:shared +full:- +full:memory (Results 1 – 25 of 327) sorted by relevance
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| /Documentation/devicetree/bindings/reserved-memory/ |
| D | xen,shared-memory.txt | 1 * Xen hypervisor reserved-memory binding
3 Expose one or more memory regions as reserved-memory to the guest
5 to be a shared memory area across multiple virtual machines for
8 For each of these pre-shared memory regions, a range is exposed under
9 the /reserved-memory node as a child node. Each range sub-node is named
10 xen-shmem@<address> and has the following properties:
12 - compatible:
13 compatible = "xen,shared-memory-v1"
15 - reg:
16 the base guest physical address and size of the shared memory region
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| D | qcom,cmd-db.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/qcom,cmd-db.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 is stored in a shared memory region and is loaded by the remote processor.
15 controlling shared resources. Depending on the board configuration the shared
17 remote processor and made available in the shared memory.
20 - Bjorn Andersson <bjorn.andersson@linaro.org>
23 - $ref: reserved-memory.yaml
27 const: qcom,cmd-db
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| /Documentation/admin-guide/mm/ |
| D | numa_memory_policy.rst | 2 NUMA Memory Policy
5 What is NUMA Memory Policy?
8 In the Linux kernel, "memory policy" determines from which node the kernel will
9 allocate memory in a NUMA system or in an emulated NUMA system. Linux has
10 supported platforms with Non-Uniform Memory Access architectures since 2.4.?.
11 The current memory policy support was added to Linux 2.6 around May 2004. This
12 document attempts to describe the concepts and APIs of the 2.6 memory policy
15 Memory policies should not be confused with cpusets
16 (``Documentation/admin-guide/cgroup-v1/cpusets.rst``)
18 memory may be allocated by a set of processes. Memory policies are a
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| D | nommu-mmap.rst | 2 No-MMU memory mapping support
5 The kernel has limited support for memory mapping under no-MMU conditions, such
6 as are used in uClinux environments. From the userspace point of view, memory
12 Memory mapping behaviour also involves the way fork(), vfork(), clone() and
16 The behaviour is similar between the MMU and no-MMU cases, but not identical;
21 In the MMU case: VM regions backed by arbitrary pages; copy-on-write
24 In the no-MMU case: VM regions backed by arbitrary contiguous runs of
30 shared across fork() or clone() without CLONE_VM in the MMU case. Since
31 the no-MMU case doesn't support these, behaviour is identical to
39 In the no-MMU case:
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| /Documentation/devicetree/bindings/sound/ |
| D | google,cros-ec-codec.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/sound/google,cros-ec-codec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cheng-Yi Chiang <cychiang@chromium.org>
11 - Tzung-Bi Shih <tzungbi@kernel.org>
15 Embedded Controller (EC) and is controlled via a host-command
17 subnode of a cros-ec node.
18 (see Documentation/devicetree/bindings/mfd/google,cros-ec.yaml).
21 - $ref: dai-common.yaml#
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| /Documentation/arch/x86/ |
| D | tdx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 encrypting the guest memory. In TDX, a special module running in a special
18 CPU-attested software module called 'the TDX module' runs inside the new
22 TDX also leverages Intel Multi-Key Total Memory Encryption (MKTME) to
23 provide crypto-protection to the VMs. TDX reserves part of MKTME KeyIDs
32 TDX boot-time detection
33 -----------------------
41 ---------------------------------------
54 use it as 'metadata' for the TDX memory. It also takes additional CPU
59 Besides initializing the TDX module, a per-cpu initialization SEAMCALL
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| D | sva.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Shared Virtual Addressing (SVA) with ENQCMD
10 Shared Virtual Addressing (SVA) allows the processor and device to use the
12 addresses to physical addresses. SVA is what PCIe calls Shared Virtual
13 Memory (SVM).
19 application page-faults. For more information please refer to the PCIe
31 Shared Hardware Workqueues
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
35 the use of Shared Work Queues (SWQ) by both applications and Virtual
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
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| /Documentation/virt/hyperv/ |
| D | overview.rst | 1 .. SPDX-License-Identifier: GPL-2.0
6 enlightened guest on Microsoft's Hyper-V hypervisor. Hyper-V
7 consists primarily of a bare-metal hypervisor plus a virtual machine
10 partitions. In this documentation, references to Hyper-V usually
15 Hyper-V runs on x86/x64 and arm64 architectures, and Linux guests
16 are supported on both. The functionality and behavior of Hyper-V is
19 Linux Guest Communication with Hyper-V
20 --------------------------------------
21 Linux guests communicate with Hyper-V in four different ways:
24 some guest actions trap to Hyper-V. Hyper-V emulates the action and
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| D | coco.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 Hyper-V can create and run Linux guests that are Confidential Computing
7 the confidentiality and integrity of data in the VM's memory, even in the
9 CoCo VMs on Hyper-V share the generic CoCo VM threat model and security
10 objectives described in Documentation/security/snp-tdx-threat-model.rst. Note
11 that Hyper-V specific code in Linux refers to CoCo VMs as "isolated VMs" or
14 A Linux CoCo VM on Hyper-V requires the cooperation and interaction of the
19 * The hardware runs a version of Windows/Hyper-V with support for CoCo VMs
25 * AMD processor with SEV-SNP. Hyper-V does not run guest VMs with AMD SME,
26 SEV, or SEV-ES encryption, and such encryption is not sufficient for a CoCo
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| /Documentation/devicetree/bindings/mailbox/ |
| D | mailbox.txt | 9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
15 #mbox-cells = <1>;
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
26 - shmem : List of phandle pointing to the shared memory(SHM) area between the
27 users of these mailboxes for IPC, one for each mailbox. This shared
28 memory can be part of any memory reserved for the purpose of this
35 mbox-names = "pwr-ctrl", "rpc";
39 Example with shared memory(shmem):
42 compatible = "mmio-sram";
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| /Documentation/userspace-api/ |
| D | unshare.rst | 10 ----------
14 --------
26 -----------
37 outside the confinement of all-or-nothing shared resources of legacy
44 shared at the time of their creation. unshare() was conceptualized by
45 Al Viro in the August of 2000, on the Linux-Kernel mailing list, as part
48 shared resources without creating a new process. unshare() is a natural
53 -----------
57 resources is not possible. Since namespaces are shared by default
59 even non-threaded applications if they have a need to disassociate
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| D | tee.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 User space (the client) connects to the driver by opening /dev/tee[0-9]* or
11 /dev/teepriv[0-9]*.
13 - TEE_IOC_SHM_ALLOC allocates shared memory and returns a file descriptor
15 descriptor any more, it should be closed. When shared memory isn't needed
17 memory.
19 - TEE_IOC_VERSION lets user space know which TEE this driver handles and
22 - TEE_IOC_OPEN_SESSION opens a new session to a Trusted Application.
24 - TEE_IOC_INVOKE invokes a function in a Trusted Application.
26 - TEE_IOC_CANCEL may cancel an ongoing TEE_IOC_OPEN_SESSION or TEE_IOC_INVOKE.
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| D | futex2.rst | 1 .. SPDX-License-Identifier: GPL-2.0
21 -----------------
40 address for ``waiters`` or for any ``uaddr`` returns ``-EFAULT``.
42 If userspace has 32-bit pointers, it should do a explicit cast to make sure
44 both 32/64-bit pointers.
47 interval will make the syscall return ``-EINVAL``.
54 return ``-EAGAIN``. If all tests and verifications succeeds, syscall waits until
57 - The timeout expires, returning ``-ETIMEOUT``.
58 - A signal was sent to the sleeping task, returning ``-ERESTARTSYS``.
59 - Some futex at the list was woken, returning the index of some waked futex.
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| /Documentation/devicetree/bindings/dma/ |
| D | fsl,imx-sdma.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,imx-sdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
10 - Joy Zou <joy.zou@nxp.com>
13 - $ref: dma-controller.yaml#
18 - items:
19 - enum:
20 - fsl,imx50-sdma
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,smem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory Manager
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 This binding describes the Qualcomm Shared Memory Manager, a region of
15 reserved-memory used to share data between various subsystems and OSes in
25 memory-region:
27 description: handle to memory reservation for main SMEM memory region.
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| D | qcom,smd.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory Driver
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The Qualcomm Shared Memory Driver is a FIFO based communication channel for
18 Using the top-level SMD node is deprecated. Instead, the SMD edges are defined
29 "^smd-edge|rpm$":
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| /Documentation/mm/ |
| D | hmm.rst | 2 Heterogeneous Memory Management (HMM)
5 Provide infrastructure and helpers to integrate non-conventional memory (device
6 memory like GPU on board memory) into regular kernel path, with the cornerstone
7 of this being specialized struct page for such memory (see sections 5 to 7 of
10 HMM also provides optional helpers for SVM (Share Virtual Memory), i.e.,
18 related to using device specific memory allocators. In the second section, I
21 CPU page-table mirroring works and the purpose of HMM in this context. The
22 fifth section deals with how device memory is represented inside the kernel.
28 Problems of using a device specific memory allocator
31 Devices with a large amount of on board memory (several gigabytes) like GPUs
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| D | overcommit-accounting.rst | 16 just relying on the virtual memory consisting almost entirely
24 killed while accessing pages but will receive errors on memory
27 Useful for applications that want to guarantee their memory
57 | SHARED or READ-only - 0 cost (the file is the map not swap)
58 | PRIVATE WRITABLE - size of mapping per instance
61 | SHARED - size of mapping
62 | PRIVATE READ-only - 0 cost (but of little use)
63 | PRIVATE WRITABLE - size of mapping per instance
67 | shmfs memory drawn from the same pool
72 * We account mmap memory mappings
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| /Documentation/driver-api/ |
| D | ntb.rst | 5 NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects
6 the separate memory systems of two or more computers to the same PCI-Express
8 registers and memory translation windows, as well as non common features like
9 scratchpad and message registers. Scratchpad registers are read-and-writable
15 Memory windows allow translated read and write access to the peer memory.
36 ----------------------------------------
38 Primary purpose of NTB is to share some peace of memory between at least two
40 mainly used to perform the proper memory window initialization. Typically
41 there are two types of memory window interfaces supported by the NTB API:
48 Memory: Local NTB Port: Peer NTB Port: Peer MMIO:
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,k3-m4f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-m4f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hari Nagalla <hnagalla@ti.com>
11 - Mathieu Poirier <mathieu.poirier@linaro.org>
20 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
25 - ti,am64-m4fss
27 power-domains:
30 "#address-cells":
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| /Documentation/filesystems/ |
| D | tmpfs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Tmpfs is a file system which keeps all of its files in virtual memory.
21 fly using a remount ('mount -o remount ...') of the filesystem. A tmpfs
26 filesystem is how much memory you have available, and so care must be taken if
27 used so to not run out of memory.
38 all tmpfs pages will be shown as "Shmem" in /proc/meminfo and "Shared" in
39 free(1). Notice that these counters also include shared memory
46 all. This is used for shared anonymous mappings and SYSV shared
47 memory.
54 POSIX shared memory (shm_open, shm_unlink). Adding the following
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| /Documentation/process/ |
| D | volatile-considered-harmful.rst | 5 ------------------------------------------------
9 sometimes tempted to use it in kernel code when shared data structures are
16 do. In the kernel, one must protect shared data structures against
19 all optimization-related problems in a more efficient way.
22 safe (spinlocks, mutexes, memory barriers, etc.) are designed to prevent
25 almost certainly a bug in the code somewhere. In properly-written kernel
38 primitives act as memory barriers - they are explicitly written to do so -
41 spin_lock() call, since it acts as a memory barrier, will force it to
49 volatile. When dealing with shared data, proper locking makes volatile
50 unnecessary - and potentially harmful.
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| /Documentation/admin-guide/cgroup-v1/ |
| D | hugetlb.rst | 7 # mount -t cgroup -o hugetlb none /sys/fs/cgroup
25 …rsvd.max_usage_in_bytes # show max "hugepagesize" hugetlb reservations and no-reserve faults
26 …hugetlb.<hugepagesize>.rsvd.usage_in_bytes # show current reservations and no-reserve f…
32 …uma_stat # show the numa information of the hugetlb memory charged to this cg…
96 HugeTLB memory for which no reservation exists. Since reservation limits are
98 the application to get SIGBUS signal if the memory was reserved before hand. For
100 limit, enforcing memory usage at fault time and causing the application to
105 never causes the application to get SIGBUS signal if the memory was reserved
107 non-HugeTLB memory for example. In the case of page fault accounting, it's very
114 3. Caveats with shared memory
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| /Documentation/devicetree/bindings/perf/ |
| D | arm,dsu-pmu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
11 - Suzuki K Poulose <suzuki.poulose@arm.com>
12 - Robin Murphy <robin.murphy@arm.com>
15 ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
16 L3 memory system, control logic and external interfaces to form a multicore
18 DSU. The PMU provides independent 32-bit counters that can count any of the
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,j721e-dss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
22 const: ti,j721e-dss
26 - description: common_m DSS Master common
27 - description: common_s0 DSS Shared common 0
28 - description: common_s1 DSS Shared common 1
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