Searched full:shift (Results 1 – 25 of 156) sorted by relevance
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| /Documentation/devicetree/bindings/mmc/ |
| D | samsung,exynos-dw-mshc.yaml | 61 - description: CIU clock phase shift value for tx mode
64 - description: CIU clock phase shift value for rx mode
68 The value of CUI clock phase shift value in transmit mode and CIU clock
69 phase shift value in receive mode for double data rate mode operation.
75 - description: CIU clock phase shift value for tx mode
78 - description: CIU clock phase shift value for rx mode
82 The value of CIU TX and RX clock phase shift value for HS400 mode
85 - valid value for tx phase shift and rx phase shift is 0 to 7.
86 - when CIU clock divider value is set to 3, all possible 8 phase shift
89 phase shift clocks should be 0.
[all …]
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| /Documentation/arch/arm/samsung/ |
| D | clksrc-change-registers.awk | 52 printf "cannot find shift " s "\n" > "/dev/stderr"
79 printf "=> '" name "' LENGTH=" dmask[name,0] " SHIFT=" dmask[name,1] "\n" > "/dev/stderr"
88 shift=""
103 if (line ~ /\.shift/) {
104 shift = extract_value(line)
121 printf "shift '" shift "' ='" dmask[shift,0] "'\n" > "/dev/stderr"
134 printf "/* shift " shift " */\n"
142 printf ".shift = " dmask[generated,1] ", "
149 printf ".shift = " dmask[mask,1] ", "
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| /Documentation/devicetree/bindings/spi/ |
| D | samsung,spi-peripheral-props.yaml | 23 The sampling phase shift to be applied on the miso line (to account
25 - 0: No phase shift.
26 - 1: 90 degree phase shift sampling.
27 - 2: 180 degree phase shift sampling.
28 - 3: 270 degree phase shift sampling.
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| /Documentation/ABI/testing/ |
| D | sysfs-firmware-opal-psr | 4 Description: Power-Shift-Ratio directory for Powernv P9 servers
6 Power-Shift-Ratio allows to provide hints the firmware
7 to shift/throttle power between different entities in
16 Power-Shift-Ratio between CPU and GPU for a given chip
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| D | debugfs-moxtet | 5 Description: (Read) Read input from the shift registers, in hexadecimal.
23 Description: (RW) Read last written value to the shift registers, in
24 hexadecimal, or write values to the shift registers, also
33 first module's shift register
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| D | sysfs-driver-hid-prodikeys | 25 Controls the octave shift modifier in the pc-midi driver.
27 0 means the no ocatve shift.
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | apll.txt | 24 - ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
25 - ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
39 ti,bit-shift = <2>;
40 ti,idlest-shift = <8>;
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| D | mux.txt | 30 the number of bits to shift the control field in the register can be
31 supplied. If the shift value is missing it is the same as supplying
32 a zero shift.
44 - ti,bit-shift : number of bits to shift the bit-mask, defaults to
68 ti,bit-shift = <24>;
76 ti,bit-shift = <4>;
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| D | gate.txt | 38 - ti,bit-shift : bit shift for programming the clock gate, invalid for
49 ti,bit-shift = <25>;
57 ti,bit-shift = <23>;
65 ti,bit-shift = <0>;
73 ti,bit-shift = <1>;
86 ti,bit-shift = <0x1b>;
95 ti,bit-shift = <3>;
103 ti,bit-shift = <15>;
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| D | divider.txt | 44 the number of bits to shift that mask, if necessary. If the shift value
45 is missing it is the same as supplying a zero shift.
62 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
71 - ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
94 ti,bit-shift = <24>;
112 ti,bit-shift = <8>;
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| D | autoidle.txt | 13 - ti,autoidle-shift : bit shift of the autoidle enable bit
22 ti,autoidle-shift = <8>;
33 ti,autoidle-shift = <8>;
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| D | interface.txt | 30 - ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
38 ti,bit-shift = <3>;
46 ti,bit-shift = <0>;
54 ti,bit-shift = <0>;
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| D | fixed-factor-clock.txt | 18 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
38 ti,autoidle-shift = <8>;
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| /Documentation/devicetree/bindings/regulator/ |
| D | anatop-regulator.yaml | 25 anatop-vol-bit-shift:
27 description: u32 value representing the bit shift for the register.
49 anatop-delay-bit-shift:
51 description: u32 value representing the bit shift for the step time register.
68 - anatop-vol-bit-shift
85 anatop-vol-bit-shift = <9>;
88 anatop-delay-bit-shift = <24>;
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| /Documentation/devicetree/bindings/clock/ |
| D | keystone-pll.txt | 45 - bit-shift : number of bits to shift the bit-mask
57 bit-shift = <23>;
67 - bit-shift : number of bits to shift the bit-mask
79 bit-shift = <0>;
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| /Documentation/devicetree/bindings/leds/backlight/ |
| D | sky81452-backlight.txt | 14 - skyworks,phase-shift : Enable phase shift mode
27 skyworks,phase-shift;
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-pisosr.txt | 1 Generic Parallel-in/Serial-out Shift Register GPIO Driver
3 This binding describes generic parallel-in/serial-out shift register
5 SN74165 serial-out shift registers and the SN65HVS88x series of
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| D | gpio-stp-xway.yaml | 11 peripheral controller used to drive external shift register cascades. At most
39 shift register cascade.
47 in the shift register cascade.
62 Use rising instead of falling edge for the shift register.
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| /Documentation/driver-api/iio/ |
| D | buffers.rst | 40 Format is [be|le]:[s|u]bits/storagebits[Xrepeat][>>shift] .
49 * *shift*, if specified, is the shift that needs to be applied prior to
71 two byte little endian signed data, that needs a 4 bits right shift before
84 u8 shift;
104 .shift = 4,
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx-anatop.yaml | 76 anatop-vol-bit-shift = <8>;
91 anatop-vol-bit-shift = <0>;
94 anatop-delay-bit-shift = <24>;
108 anatop-vol-bit-shift = <18>;
111 anatop-delay-bit-shift = <28>;
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| /Documentation/devicetree/bindings/i2c/ |
| D | opencores,i2c-ocores.yaml | 57 reg-shift:
65 deprecated, use reg-shift above
98 reg-shift = <0>; /* 8 bit registers */
111 reg-shift = <0>; /* 8 bit registers */
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| /Documentation/netlink/specs/ |
| D | tcp_metrics.yaml | 97 (left-shift by 3 to get the msec value).
103 (left-shift by 2 to get the msec value).
121 (left-shift by 3 to get the msec value).
127 (left-shift by 3 to get the msec value).
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| /Documentation/devicetree/bindings/net/ |
| D | socfpga-dwmac.txt | 15 encompasses the glue register, the register offset, and the register shift.
16 On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
17 on the Arria10/Stratix10/Agilex platforms, the register shift represents
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| /Documentation/devicetree/bindings/serial/ |
| D | 8250.yaml | 33 reg-shift:
36 - reg-shift
150 reg-shift:
151 description: Quantity to shift the register offsets by.
233 reg-shift = <2>;
256 reg-shift = <2>;
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | ovti,ov772x.yaml | 57 data-shift:
89 data-shift:
127 data-shift = <0>;
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