Searched +full:single +full:- +full:bit (Results 1 – 25 of 542) sorted by relevance
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| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 3 The ECC Manager counts and corrects single bit errors and counts/handles
4 double bit errors which are uncorrectable.
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
24 - compatible : Should be "altr,socfpga-ocram-ecc"
[all …]
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| D | aspeed-sdram-edac.txt | 6 The memory controller supports SECDED (single bit error correction, double bit
7 error detection) and single bit error auto scrubbing by reserving 8 bits for
8 every 64 bit word (effectively reducing available memory to 8/9).
14 - compatible: should be one of
15 - "aspeed,ast2400-sdram-edac"
16 - "aspeed,ast2500-sdram-edac"
17 - "aspeed,ast2600-sdram-edac"
18 - reg: sdram controller register set should be <0x1e6e0000 0x174>
19 - interrupts: should be AVIC interrupt #0
25 compatible = "aspeed,ast2500-sdram-edac";
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| /Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - acbel,fsg032
35 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
36 - ad,ad7414 # Deprecated, use adi,ad7414
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| /Documentation/gpu/ |
| D | afbc.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
37 reside in the least-significant bits of the corresponding linear
81 Formats which are typically multi-planar in linear layouts (e.g. YUV
111 Cross-device interoperability
115 canonical formats for use between AFBC-enabled devices. Formats which
119 .. flat-table:: AFBC formats
121 * - Fourcc code
122 - Description
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| /Documentation/devicetree/bindings/timer/ |
| D | nvidia,tegra-timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
21 # Either a single combined interrupt or up to 14 individual interrupts
27 - if:
31 - items:
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| /Documentation/hwmon/ |
| D | pcf8591.rst | 17 - Aurelien Jarno <aurelien@aurel32.net>
18 - valuable contributions by Jan M. Sendler <sendler@sendler.de>,
19 - Jean Delvare <jdelvare@suse.de>
23 -----------
25 The PCF8591 is an 8-bit A/D and D/A converter (4 analog inputs and one
29 The PCF8591 has 4 analog inputs programmable as single-ended or
32 - mode 0 : four single ended inputs
33 Pins AIN0 to AIN3 are single ended inputs for channels 0 to 3
35 - mode 1 : three differential inputs
39 - mode 2 : single ended and differential mixed
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| D | ads7828.rst | 6 * Texas Instruments/Burr-Brown ADS7828
23 - Steve Hardy <shardy@redhat.com>
24 - Vivien Didelot <vivien.didelot@savoirfairelinux.com>
25 - Guillaume Roguez <guillaume.roguez@savoirfairelinux.com>
28 -------------
34 set to true for differential mode, false for default single ended mode.
45 If no structure is provided, the configuration defaults to single ended
49 -----------
53 The ADS7828 device is a 12-bit 8-channel A/D converter, while the ADS7830 does
54 8-bit sampling.
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec2.txt | 1 Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
5 - compatible : Should contain entries for this and backward compatible
9 - reg : Offset and length of the register set for the device
10 - interrupts : the SEC's interrupt number
11 - fsl,num-channels : An integer representing the number of channels
13 - fsl,channel-fifo-len : An integer representing the number of
15 - fsl,exec-units-mask : The bitmask representing what execution units
16 (EUs) are available. It's a single 32-bit cell. EU information
20 bit 0 = reserved - should be 0
21 bit 1 = set if SEC has the ARC4 EU (AFEU)
[all …]
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-single.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Controller with a Single Register for One or More Pins
10 - Tony Lindgren <tony@atomide.com>
13 Some pin controller devices use a single register for one or more pins. The
21 - enum:
22 - pinctrl-single
23 - pinconf-single
[all …]
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| /Documentation/devicetree/bindings/arm/ |
| D | qcom,coresight-tpdm.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Trace, Profiling and Diagnostics Monitor - TPDM
13 Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
14 Single Bit (DSB). It performs data collection in the data producing clock
22 - Mao Jinlong <quic_jinlmao@quicinc.com>
23 - Tao Zhang <quic_taozha@quicinc.com>
31 - qcom,coresight-tpdm
[all …]
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| /Documentation/networking/ |
| D | oa-tc6-framework.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
15 single balanced pair of conductors, or half duplex multidrop bus
16 operation over 25 m of single balanced pair of conductors.
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
[all …]
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| /Documentation/devicetree/bindings/leds/ |
| D | register-bit-led.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/register-bit-led.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Register Bit LEDs
10 - Linus Walleij <linus.walleij@linaro.org>
13 Register bit leds are used with syscon multifunctional devices where single
14 bits in a certain register can turn on/off a single LED. The register bit LEDs
20 - $ref: /schemas/leds/common.yaml#
25 The unit-address is in the form of @<reg addr>,<bit offset>
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,vic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
15 be nested or have the outputs wire-OR'd together.
18 - $ref: /schemas/interrupt-controller.yaml#
23 - arm,pl190-vic
24 - arm,pl192-vic
25 - arm,versatile-vic
[all …]
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| D | st,spear3xx-shirq.txt | 4 of devices. The multiplexor provides a single interrupt to parent
10 bit masks. Also in some cases the group may not have enable or other
13 A single node in the device tree is used to describe the shared
16 For example, a 32-bit interrupt enable/disable config register can
20 - compatible: should be, either of
21 - "st,spear300-shirq"
22 - "st,spear310-shirq"
23 - "st,spear320-shirq"
24 - interrupt-controller: Identifies the node as an interrupt controller.
25 - #interrupt-cells: should be <1> which basically contains the offset
[all …]
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| /Documentation/ |
| D | atomic_bitops.txt | 5 While our bitmap_{}() functions are non-atomic, we have a number of operations
6 operating on single bits in a bitmap that are atomic.
10 ---
12 The single bit operations are:
14 Non-RMW ops:
33 All RMW atomic operations have a '__' prefixed variant which is non-atomic.
37 ---------
39 Non-atomic ops:
47 The test_and_{}_bit() operations return the original value of the bit.
51 --------
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| /Documentation/devicetree/bindings/media/ |
| D | ti,da850-vpif.txt | 2 ----------------------
12 - compatible: must be "ti,da850-vpif"
13 - reg: physical base address and length of the registers set for the device;
14 - interrupts: should contain IRQ line for the VPIF
18 VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a
19 single 16-bit channel. It should contain one or two port child nodes
23 Documentation/devicetree/bindings/media/video-interfaces.txt.
25 Example using 2 8-bit input channels, one of which is connected to an
26 I2C-connected TVP5147 decoder:
29 compatible = "ti,da850-vpif";
[all …]
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| /Documentation/fb/ |
| D | viafb.rst | 6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
[all …]
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| /Documentation/i2c/ |
| D | ten-bit-addresses.rst | 2 I2C Ten-bit Addresses
5 The I2C protocol knows about two kinds of device addresses: normal 7 bit
6 addresses, and an extended set of 10 bit addresses. The sets of addresses
7 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
8 address 0x10 (though a single device could respond to both of them).
9 To avoid ambiguity, the user sees 10 bit addresses mapped to a different
10 address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
11 10 bit mode. This is used for creating device names in sysfs. It is also
12 needed when instantiating 10 bit devices via the new_device file in sysfs.
14 I2C messages to and from 10-bit address devices have a different format.
[all …]
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| D | smbus-protocol.rst | 24 single data byte, the functions using SMBus protocol operation names execute
42 Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
43 A, NA (1 bit) Acknowledge (ACK) and Not Acknowledge (NACK) bit
44 Addr (7 bits) I2C 7 bit address. Note that this can be expanded to
45 get a 10 bit I2C address.
49 high byte of a 16 bit word.
60 This sends a single bit to the device, at the place of the Rd/Wr bit::
72 This reads a single byte from a device, without specifying a device
87 This operation is the reverse of Receive Byte: it sends a single byte
102 This reads a single byte from a device, from a designated register.
[all …]
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| /Documentation/trace/coresight/ |
| D | coresight-etm4x-reference.rst | 11 ---------------------------
20 ----
25 Bit select trace features. See ‘mode’ section below. Bits
37 ----
47 ----
52 - > 0 : Programs up the hardware with the current values held in the driver
55 - = 0 : disable trace hardware.
60 ----
72 ----
77 When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for trace session. Otherwise -1
[all …]
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | maxim,max1241.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Maxim MAX1241 12-bit, single-channel analog to digital converter
11 - Alexandru Lazar <alazar@startmail.com>
14 Bindings for the max1241 12-bit, single-channel ADC device. Datasheet
16 https://datasheets.maximintegrated.com/en/ds/MAX1240-MAX1241.pdf
21 - maxim,max1241
26 vdd-supply:
30 vref-supply:
[all …]
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-tegra-fuse | 1 What: /sys/devices/*/<our-device>/fuse
4 Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114
6 data programmed at the factory. The data is laid out in 32bit
7 words in LSB first format. Each bit represents a single value
|
| /Documentation/devicetree/bindings/memory-controllers/ |
| D | xlnx,zynq-ddrc-a05.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
14 The Zynq DDR ECC controller has an optional ECC support in half-bus width
15 (16-bit) configuration. It is capable of correcting single bit ECC errors
16 and detecting double bit ECC errors.
20 const: xlnx,zynq-ddrc-a05
[all …]
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| /Documentation/arch/mips/ |
| D | booting.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ------------------------
6 Some bootloaders only support a single entry point, at the start of the
11 Similar to the arch/arm case (b), a DT-aware bootloader is expected to
20 512MB of the physical address space (0x00000000 - 0x1fffffff),
21 aligned on a 64 bit boundary.
27 This convention is defined for 32-bit systems only, as there are not
28 currently any 64-bit BMIPS implementations.
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| /Documentation/devicetree/bindings/iommu/ |
| D | apple,sart.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sven Peter <sven@svenpeter.dev>
17 transactions of a single device are subject to SART filtering.
20 and allows 36 bit of physical address space and filter entries with sizes
21 up to 24 bit.
23 SART2, first seen in A14 and M1, allows 36 bit of physical address space
24 and filter entry size up to 36 bit.
27 entry size to 42 bit.
[all …]
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