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/Documentation/devicetree/bindings/rtc/
Dmarvell,armada-380-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/marvell,armada-380-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RTC controller for the Armada 38x, 7K and 8K SoCs
10 - Javier Carrasco <javier.carrasco.cruz@gmail.com>
13 - $ref: rtc.yaml#
18 - marvell,armada-380-rtc
19 - marvell,armada-8k-rtc
23 - description: RTC base address size
[all …]
Dmediatek,mt7622-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/rtc/mediatek,mt7622-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7622 on-SoC RTC
10 - $ref: rtc.yaml#
13 - Sean Wang <sean.wang@mediatek.com>
18 - const: mediatek,mt7622-rtc
19 - const: mediatek,soc-rtc
30 clock-names:
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Drtc-omap.txt4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
19 - clock-names: Corresponding names of the clocks
[all …]
Dmicrochip,mfps-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip PolarFire Soc (MPFS) RTC
11 - $ref: rtc.yaml#
14 - Daire McNamara <daire.mcnamara@microchip.com>
15 - Lewis Hanly <lewis.hanly@microchip.com>
20 - microchip,mpfs-rtc
27 - description: |
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Drtc-mt6397.txt1 Device-Tree bindings for MediaTek PMIC based RTC
3 MediaTek PMIC based RTC is an independent function of MediaTek PMIC that works
4 as a type of multi-function device (MFD). The RTC can be configured and set up
12 ../soc/mediatek/pwrap.txt
15 - compatible: Should be one of follows
16 "mediatek,mt6323-rtc": for MT6323 PMIC
17 "mediatek,mt6358-rtc": for MT6358 PMIC
18 "mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC
19 "mediatek,mt6397-rtc": for MT6397 PMIC
28 rtc {
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Dmediatek,mt2712-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/rtc/mediatek,mt2712-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT2712 on-SoC RTC
10 - $ref: rtc.yaml#
13 - Ran Bi <ran.bi@mediatek.com>
17 const: mediatek,mt2712-rtc
26 - reg
27 - interrupts
[all …]
Drtc-mxc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/rtc-mxc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: rtc.yaml#
13 - Philippe Reynes <tremyfr@gmail.com>
18 - fsl,imx1-rtc
19 - fsl,imx21-rtc
29 - description: input reference
30 - description: the SoC RTC clock
[all …]
Dalphascale,asm9260-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/alphascale,asm9260-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Alphascale asm9260 SoC Real Time Clock
10 - Javier Carrasco <javier.carrasco.cruz@gmail.com>
13 - $ref: rtc.yaml#
17 const: alphascale,asm9260-rtc
25 clock-names:
32 - compatible
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Dxlnx,zynqmp-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
11 The RTC controller has separate IRQ lines for seconds and alarm.
14 - Michal Simek <michal.simek@amd.com>
17 - $ref: rtc.yaml#
22 - const: xlnx,zynqmp-rtc
23 - items:
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Drenesas,sh-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/renesas,sh-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - const: renesas,r7s72100-rtc # RZ/A1H
17 - const: renesas,sh-rtc
25 interrupt-names:
27 - const: alarm
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Dtrivial-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/trivial-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 This is a list of trivial RTC devices that have simple device tree
18 - $ref: rtc.yaml#
23 # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
24 - abracon,abb5zes3
25 # AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
[all …]
Disil,isl12057.txt1 Intersil ISL12057 I2C RTC/Alarm chip
8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
12 to the SoC but to a PMIC. It allows the device to be powered up when
13 RTC alarm rings. In order to mark the device has a wakeup source and
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
20 - "compatible": must be "isil,isl12057"
21 - "reg": I2C bus address of the device
25 - "wakeup-source": mark the chip as a wakeup source, independently of
[all …]
Dfsl,ls-ftm-alarm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/fsl,ls-ftm-alarm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - fsl,ls1012a-ftm-alarm
16 - fsl,ls1021a-ftm-alarm
17 - fsl,ls1028a-ftm-alarm
18 - fsl,ls1043a-ftm-alarm
19 - fsl,ls1046a-ftm-alarm
[all …]
/Documentation/devicetree/bindings/regulator/
Dnvidia,tegra-regulators-coupling.txt4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
9 ------------------------
11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
16 ------------------------
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
27 as the "RTC domain" voltage regulator.
28 - nvidia,tegra-cpu-regulator: Boolean property that designates regulator
[all …]
/Documentation/devicetree/bindings/timer/
Dsnps,archs-rtc.txt1 Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
2 - clocksource provider for UP SoC
6 - compatible : should be "snps,archs-rtc"
7 - clocks : phandle to the source clock
11 rtc {
12 compatible = "snps,arc-rtc";
/Documentation/admin-guide/
Drtc.rst2 Real Time Clock (RTC) Drivers for Linux
8 the local time zone or daylight savings time -- unless they dual boot
9 with MS-Windows -- but will instead be set to Coordinated Universal Time
12 The newest non-PC hardware tends to just count seconds, like the time(2)
16 Linux has two largely-compatible userspace RTC API families you may
19 * /dev/rtc ... is the RTC provided by PC compatible systems,
20 so it's not very portable to non-x86 systems.
23 supported by a wide variety of RTC chips on all systems.
27 RTCs use the same API to make requests in both RTC frameworks (using
29 same functionality. For example, not every RTC is hooked up to an
[all …]
/Documentation/devicetree/bindings/clock/
Dlpc1850-creg-clk.txt8 These clocks are used by the RTC and the Event Router peripherals.
13 Documentation/devicetree/bindings/clock/clock-bindings.txt
16 - compatible:
17 Should be "nxp,lpc1850-creg-clk"
18 - #clock-cells:
20 - clocks:
23 The creg-clk node must be a child of the creg syscon node.
32 soc {
34 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
37 creg_clk: clock-controller {
[all …]
Drockchip,rk3308-cru.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
15 controllers within the SoC and also implements a reset controller for SoC
19 preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
22 There are several clocks that are generated outside the SoC. It is expected
24 clock-output-names:
[all …]
Drockchip,rk3188-cru.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
15 controllers within the SoC and also implements a reset controller for SoC
19 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
20 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
22 There are several clocks that are generated outside the SoC. It is expected
[all …]
Drockchip,rk3368-cru.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
15 controllers within the SoC and also implements a reset controller for SoC
19 preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
22 There are several clocks that are generated outside the SoC. It is expected
24 clock-output-names:
[all …]
Drockchip,rk3288-cru.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
15 controllers within the SoC and also implements a reset controller for SoC
18 A revision of this SoC is available: rk3288w. The clock tree is a bit
19 different so another dt-compatible is available. Noticed that it is only
25 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
[all …]
Drockchip,rk3399-cru.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
15 controllers within the SoC and also implements a reset controller for SoC
19 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
22 There are several clocks that are generated outside the SoC. It is expected
24 clock-output-names:
[all …]
/Documentation/devicetree/bindings/mfd/
Dmt6397.txt4 - Regulator
5 - RTC
6 - Audio codec
7 - GPIO
8 - Clock
9 - LED
10 - Keys
11 - Power controller
16 ../soc/mediatek/mediatek,pwrap.yaml
32 - rtc
[all …]
Dmediatek,mt6357.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Flora Fu <flora.fu@mediatek.com>
11 - Alexandre Mergnat <amergnat@baylibre.com>
16 USB battery charging, fuel gauge, RTC
19 - Regulator
20 - RTC
21 - Keys
26 Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dcortina,gemini-pinctrl.txt3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
10 - compatible: "cortina,gemini-pinctrl"
12 Subnodes of the pin controller contain pin control multiplexing set-up
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
19 - skew-delay is supported on the Ethernet pins
20 - drive-strength with 4, 8, 12 or 16 mA as argument is supported for
28 compatible = "cortina,gemini-syscon";
31 compatible = "cortina,gemini-pinctrl";
32 pinctrl-names = "default";
[all …]

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