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/Documentation/devicetree/bindings/pinctrl/
Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
25 mpp1 1 gpo, nand(io3), spi(mosi)
26 mpp2 2 gpo, nand(io4), spi(sck)
[all …]
Dpinctrl-mcp23s08.txt2 8-/16-bit I/O expander with serial interface (I2C/SPI)
5 - compatible : Should be
6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version
7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or
9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
11 - "microchip,mcp23s08" for 8 GPIO SPI version
12 - "microchip,mcp23s17" for 16 GPIO SPI version
13 - "microchip,mcp23s18" for 16 GPIO SPI version
14 - "microchip,mcp23008" for 8 GPIO I2C version or
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/Documentation/devicetree/bindings/spi/
Dspi-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
14 dedicated GPIO lines.
17 - $ref: /schemas/spi/spi-controller.yaml#
21 const: spi-gpio
[all …]
Dbrcm,bcm2835-aux-spi.txt3 The BCM2835 contains two forms of SPI master controller, one known simply as
4 SPI0, and the other known as the "Universal SPI Master"; part of the
8 - compatible: Should be "brcm,bcm2835-aux-spi".
9 - reg: Should contain register location and length for the spi block
10 - interrupts: Should contain shared interrupt of the aux block
11 - clocks: The clock feeding the SPI controller - needs to
15 - cs-gpios: the cs-gpios (native cs is NOT supported)
16 see also spi-bus.txt
21 compatible = "brcm,bcm2835-aux-spi";
25 #address-cells = <1>;
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/Documentation/devicetree/bindings/display/panel/
Dsamsung,lms397kf04.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Linus Walleij <linus.walleij@linaro.org>
16 - $ref: panel-common.yaml#
17 - $ref: /schemas/spi/spi-peripheral-props.yaml#
26 reset-gpios: true
28 vci-supply:
32 vccio-supply:
38 spi-cpha: true
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Dsamsung,s6d27a1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Markuss Broks <markuss.broks@gmail.com>
16 - $ref: panel-common.yaml#
17 - $ref: /schemas/spi/spi-peripheral-props.yaml#
33 reset-gpios: true
35 vci-supply:
39 vccio-supply:
45 spi-cpha: true
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Dsamsung,lms380kf01.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Linus Walleij <linus.walleij@linaro.org>
17 - $ref: panel-common.yaml#
18 - $ref: /schemas/spi/spi-peripheral-props.yaml#
34 reset-gpios: true
36 vci-supply:
40 vccio-supply:
46 spi-cpha: true
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/Documentation/devicetree/bindings/gpio/
Dgpio-pisosr.txt1 Generic Parallel-in/Serial-out Shift Register GPIO Driver
3 This binding describes generic parallel-in/serial-out shift register
5 SN74165 serial-out shift registers and the SN65HVS88x series of
9 - compatible : Should be "pisosr-gpio".
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two. For consumer use see gpio.txt.
14 - ngpios : Number of used GPIO lines (0..n-1), default is 8.
15 - load-gpios : GPIO pin specifier attached to load enable, this
19 For other required and optional properties of SPI slave
20 nodes please refer to ../spi/spi-bus.txt.
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Dgpio-xra1403.txt1 GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR
3 The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available:
4 - Individually programmable inputs:
5 - Internal pull-up resistors
6 - Polarity inversion
7 - Individual interrupt enable
8 - Rising edge and/or Falling edge interrupt
9 - Input filter
10 - Individually programmable outputs
11 - Output Level Control
[all …]
Dfairchild,74hc595.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic 8-bit shift register
10 - Maxime Ripard <mripard@kernel.org>
15 - fairchild,74hc595
16 - nxp,74lvc594
21 gpio-controller: true
23 '#gpio-cells':
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/Documentation/devicetree/bindings/mmc/
Dmmc-spi-slot.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-spi-slot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMC/SD/SDIO slot directly connected to a SPI bus
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml
14 - $ref: /schemas/spi/spi-peripheral-props.yaml
17 The extra properties used by an mmc connected via SPI.
21 const: mmc-spi-slot
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/Documentation/devicetree/bindings/net/nfc/
Dmarvell,nci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - marvell,nfc-i2c
16 - marvell,nfc-spi
17 - marvell,nfc-uart
19 hci-muxed:
30 reset-n-io:
31 $ref: /schemas/types.yaml#/definitions/phandle-array
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Dst,st95hf.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
16 enable-gpio:
17 description: Output GPIO pin used for enabling/disabling the controller
25 st95hfvin-supply:
29 - compatible
30 - enable-gpio
31 - interrupts
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/Documentation/devicetree/bindings/fpga/
Dlattice-ice40-fpga-mgr.txt4 - compatible: Should contain "lattice,ice40-fpga-mgr"
5 - reg: SPI chip select
6 - spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
7 - cdone-gpios: GPIO input connected to CDONE pin
8 - reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note
9 that unless the GPIO is held low during startup, the
10 FPGA will enter Master SPI mode and drive SCK with a
16 compatible = "lattice,ice40-fpga-mgr";
18 spi-max-frequency = <1000000>;
19 cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
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/Documentation/devicetree/bindings/sound/
Drenesas,idt821034.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
16 The time-slots used by the codec must be set and so, the properties
17 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
18 'dai-tdm-slot-rx-mask' must be present in the ALSA sound card node for
19 sub-nodes that involve the codec. The codec uses one 8bit time-slot per
21 'dai-tdm-tdm-slot-with' must be set to 8.
26 - $ref: /schemas/spi/spi-peripheral-props.yaml#
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Dinfineon,peb2466.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
13 The Infineon PEB2466 codec is a programmable DSP-based four channels codec
16 The time-slots used by the codec must be set and so, the properties
17 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
18 'dai-tdm-slot-rx-mask' must be present in the sound card node for sub-nodes
19 that involve the codec. The codec uses one 8bit time-slot per channel.
20 'dai-tdm-tdm-slot-with' must be set to 8.
[all …]
/Documentation/devicetree/bindings/net/ieee802154/
Dca8210.txt4 - compatible: Should be "cascoda,ca8210"
5 - reg: Controlling chip select
6 - spi-max-frequency: Maximum clock speed, should be *less than*
8 - spi-cpol: Requires inverted clock polarity
9 - reset-gpio: GPIO attached to reset
10 - irq-gpio: GPIO attached to IRQ
12 - extclock-enable: Include for the ca8210 to route its 16MHz clock
14 - extclock-freq: Frequency in Hz of the external clock
15 - extclock-gpio: GPIO of the ca8210 to output the clock on
21 spi-max-frequency = <3000000>;
[all …]
/Documentation/devicetree/bindings/bus/
Dmoxtet.txt1 Turris Mox module status and configuration bus (over SPI)
4 - compatible : Should be "cznic,moxtet"
5 - #address-cells : Has to be 1
6 - #size-cells : Has to be 0
7 - spi-cpol : Required inverted clock polarity
8 - spi-cpha : Required shifted clock phase
9 - interrupts : Must contain reference to the shared interrupt line
10 - interrupt-controller : Required
11 - #interrupt-cells : Has to be 1
13 For other required and optional properties of SPI slave nodes please refer to
[all …]
/Documentation/devicetree/bindings/net/wireless/
Dti,wl1251.txt3 The wl1251 chip can be connected via SPI or via SDIO. This
4 document describes the binding for the SPI connected chip.
7 - compatible : Should be "ti,wl1251"
8 - reg : Chip select address of device
9 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
10 - interrupts : Should contain interrupt line
11 - vio-supply : phandle to regulator providing VIO
14 - ti,wl1251-has-eeprom : boolean, the wl1251 has an eeprom connected, which
16 - ti,power-gpio : GPIO connected to chip's PMEN pin if operated in
17 SPI mode
[all …]
Dsilabs,wfx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jérôme Pouiller <jerome.pouiller@silabs.com>
16 https://www.silabs.com/documents/public/data-sheets/wf200-datasheet.pdf
18 The WF200 can be connected via SPI or via SDIO.
25 It is recommended to declare a mmc-pwrseq on SDIO host above WFx. Without
26 it, you may encounter issues during reboot. The mmc-pwrseq should be
27 compatible with mmc-pwrseq-simple. Please consult
28 Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml for more
[all …]
/Documentation/devicetree/bindings/misc/
Dolpc,xo1.75-ec.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/misc/olpc,xo1.75-ec.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: OLPC XO-1.75 Embedded Controller
11 This binding describes the Embedded Controller acting as a SPI bus master
12 on a OLPC XO-1.75 laptop computer.
14 The embedded controller requires the SPI controller driver to signal
17 "ready-gpios" property of the SSP binding as documented in:
18 <Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml>.
[all …]
/Documentation/devicetree/bindings/iio/accel/
Dadi,adxl345.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADXL345/ADXL375 3-Axis Digital Accelerometers
10 - Michael Hennerich <michael.hennerich@analog.com>
13 Analog Devices ADXL345/ADXL375 3-Axis Digital Accelerometers that supports
14 both I2C & SPI interfaces.
16 https://www.analog.com/en/products/sensors-mems/accelerometers/adxl375.html
21 - items:
22 - const: adi,adxl346
[all …]
/Documentation/devicetree/bindings/net/
Dwiznet,w5x00.txt3 This is a standalone 10/100 MBit Ethernet controller with SPI interface.
5 For each device connected to a SPI bus, define a child node within
6 the SPI master node.
9 - compatible: Should be one of the following strings:
13 - reg: Specify the SPI chip select the chip is wired to.
14 - interrupts: Specify the interrupt index within the interrupt controller (referred
15 to above in interrupt-parent) and interrupt type. w5x00 natively
18 - pinctrl-names: List of assigned state names, see pinctrl binding documentation.
19 - pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
24 - spi-max-frequency: Maximum frequency of the SPI bus when accessing the w5500.
[all …]
Ddavicom,dm9051.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Davicom DM9051 SPI Ethernet Controller
10 - Joseph CHANG <josright123@gmail.com>
13 The DM9051 is a fully integrated and cost-effective low pin count single
14 chip Fast Ethernet controller with a Serial Peripheral Interface (SPI).
17 - $ref: ethernet-controller.yaml#
26 spi-max-frequency:
32 local-mac-address: true
[all …]
/Documentation/devicetree/bindings/mfd/
Daltera-a10sr.txt4 - compatible : "altr,a10sr"
5 - spi-max-frequency : Maximum SPI frequency.
6 - reg : The SPI Chip Select address for the Arria10
8 - interrupts : The interrupt line the device is connected to.
9 - interrupt-controller : Marks the device node as an interrupt controller.
10 - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
13 masks from ../interrupt-controller/interrupts.txt.
15 The A10SR consists of these sub-devices:
18 ------ ----------
19 a10sr_gpio GPIO Controller
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