Home
last modified time | relevance | path

Searched +full:spi +full:- +full:slave (Results 1 – 25 of 60) sorted by relevance

123

/Documentation/devicetree/bindings/spi/
Dmediatek,spi-slave-mt27xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-slave-mt27xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Slave controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - mediatek,mt2712-spi-slave
19 - mediatek,mt8195-spi-slave
30 clock-names:
[all …]
Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
4 memory register, which acts as an SPI master device.
6 The device uses the standard MicroWire half-duplex transfer timing.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
21 Requirements to SPI slave nodes:
23 - There can be only one slave device.
[all …]
Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Common Properties
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
[all …]
Dspi-sunplus-sp7021.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/spi/spi-sunplus-sp7021.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus sp7021 SPI controller
11 - $ref: spi-controller.yaml
14 - Li-hao Kuo <lhjeff911@gmail.com>
19 - sunplus,sp7021-spi
23 - description: the SPI master registers
24 - description: the SPI slave registers
[all …]
Dspi-davinci.txt1 Davinci SPI controller device bindings
4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
10 address on the SPI bus. Should be set to 1.
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
[all …]
Dmarvell,mmp2-ssp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/spi/marvell,mmp2-ssp.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: PXA2xx SSP SPI Controller
11 - Lubomir Rintel <lkundrak@v3.sk>
16 - marvell,mmp2-ssp
17 - mrvl,ce4100-ssp
18 - mvrl,pxa168-ssp
19 - mrvl,pxa25x-ssp
[all …]
Dmediatek,spi-mtk-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
17 for devices other than SPI NOR flash due to limited transfer
[all …]
Dnvidia,tegra210-quad-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral properties for Tegra Quad SPI Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 nvidia,tx-clk-tap-delay:
18 QSPI to corresponding slave device.
23 nvidia,rx-clk-tap-delay:
[all …]
Drenesas,rzv2m-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 - $ref: spi-controller.yaml#
18 const: renesas,rzv2m-csi
28 - description: The clock used to generate the output clock (CSICLK)
29 - description: Internal clock to access the registers (PCLK)
[all …]
Dspi-sprd.txt1 Spreadtrum SPI Controller
4 - compatible: Should be "sprd,sc9860-spi".
5 - reg: Offset and length of SPI controller register space.
6 - interrupts: Should contain SPI interrupt.
7 - clock-names: Should contain following entries:
8 "spi" for SPI clock,
9 "source" for SPI source (parent) clock,
10 "enable" for SPI module enable clock.
11 - clocks: List of clock input name strings sorted in the same order
12 as the clock-names property.
[all …]
Dbrcm,spi-bcm-qspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPI controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
17 MSPI : SPI master controller can read and write to a SPI slave device
[all …]
Dspi-fsl-lpspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Low Power SPI (LPSPI) for i.MX
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: /schemas/spi/spi-controller.yaml#
20 - enum:
[all …]
/Documentation/devicetree/bindings/fpga/
Dlattice-machxo2-spi.txt1 Lattice MachXO2 Slave SPI FPGA Manager
4 'slave SPI' interface.
9 - compatible: should contain "lattice,machxo2-slave-spi"
10 - reg: spi chip select of the FPGA
14 fpga-region0 {
15 compatible = "fpga-region";
16 fpga-mgr = <&fpga_mgr_spi>;
17 #address-cells = <0x1>;
18 #size-cells = <0x1>;
21 spi1: spi@2000 {
[all …]
Dxlnx,fpga-slave-serial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Slave Serial SPI FPGA
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
14 over what is referred to as slave serial interface.The slave serial link is
15 not technically SPI, and might require extra circuits in order to play nicely
16 with other SPI slaves on the same bus.
[all …]
Dlattice,sysconfig.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lattice Slave SPI sysCONFIG FPGA manager
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
14 have Slave Serial Peripheral Interface. Only full reconfiguration is
23 - lattice,sysconfig-ecp5
28 program-gpios:
34 init-gpios:
40 done-gpios:
[all …]
Dmicrochip,mpf-spi-fpga-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
19 - microchip,mpf-spi-fpga-mgr
22 description: SPI chip select
26 - compatible
27 - reg
[all …]
/Documentation/devicetree/bindings/misc/
Dolpc,xo1.75-ec.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/misc/olpc,xo1.75-ec.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: OLPC XO-1.75 Embedded Controller
11 This binding describes the Embedded Controller acting as a SPI bus master
12 on a OLPC XO-1.75 laptop computer.
14 The embedded controller requires the SPI controller driver to signal
17 "ready-gpios" property of the SSP binding as documented in:
18 <Documentation/devicetree/bindings/spi/marvell,mmp2-ssp.yaml>.
[all …]
Dlwn-bk4.txt1 * Liebherr's BK4 controller external SPI
5 The SPI is used for data and management purposes in both master and
6 slave modes.
10 - compatible : Should be "lwn,bk4"
12 Required SPI properties:
14 - reg : Should be address of the device chip select within
17 - spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
22 spidev0: spi@0 {
24 spi-max-frequency = <30000000>;
/Documentation/driver-api/
Dspi.rst1 Serial Peripheral Interface (SPI)
4 SPI is the "Serial Peripheral Interface", widely used with embedded
7 often in the range of 1-20 MHz), a "Master Out, Slave In" (MOSI) data
8 line, and a "Master In, Slave Out" (MISO) data line. SPI is a full
12 additional chipselect line is usually active-low (nCS); four signals are
15 The SPI bus facilities listed here provide a generalized interface to
16 declare SPI busses and devices, manage them according to the standard
18 only "master" side interfaces are supported, where Linux talks to SPI
20 to support implementing SPI slaves would necessarily look different.)
26 SPI shift register (maximizing throughput). Such drivers bridge between
[all …]
/Documentation/devicetree/bindings/net/
Dqca,qca7000.txt3 The QCA7000 is a serial-to-powerline bridge with a host interface which could
4 be configured either as SPI or UART slave. This configuration is done by
7 (a) Ethernet over SPI
9 In order to use the QCA7000 as SPI device it must be defined as a child of a
10 SPI master in the device tree.
13 - compatible : Should be "qca,qca7000"
14 - reg : Should specify the SPI chip select
15 - interrupts : The first cell should specify the index of the source
18 - spi-cpha : Must be set
19 - spi-cpol : Must be set
[all …]
/Documentation/devicetree/bindings/display/panel/
Dlg,lg4573.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LG LG4573 TFT Liquid Crystal Display with SPI control bus
10 The panel must obey the rules for a SPI slave device as specified in
11 spi/spi-controller.yaml
14 - Heiko Schocher <hs@denx.de>
17 - $ref: panel-common.yaml#
18 - $ref: /schemas/spi/spi-peripheral-props.yaml#
28 - compatible
[all …]
/Documentation/devicetree/bindings/bus/
Dmoxtet.txt1 Turris Mox module status and configuration bus (over SPI)
4 - compatible : Should be "cznic,moxtet"
5 - #address-cells : Has to be 1
6 - #size-cells : Has to be 0
7 - spi-cpol : Required inverted clock polarity
8 - spi-cpha : Required shifted clock phase
9 - interrupts : Must contain reference to the shared interrupt line
10 - interrupt-controller : Required
11 - #interrupt-cells : Has to be 1
13 For other required and optional properties of SPI slave nodes please refer to
[all …]
/Documentation/devicetree/bindings/gpio/
Dgpio-pisosr.txt1 Generic Parallel-in/Serial-out Shift Register GPIO Driver
3 This binding describes generic parallel-in/serial-out shift register
5 SN74165 serial-out shift registers and the SN65HVS88x series of
9 - compatible : Should be "pisosr-gpio".
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two. For consumer use see gpio.txt.
14 - ngpios : Number of used GPIO lines (0..n-1), default is 8.
15 - load-gpios : GPIO pin specifier attached to load enable, this
19 For other required and optional properties of SPI slave
20 nodes please refer to ../spi/spi-bus.txt.
[all …]
/Documentation/devicetree/bindings/fsi/
Dibm,fsi2spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-or-later)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: IBM FSI-attached SPI controllers
10 - Eddie James <eajames@linux.ibm.com>
15 access to a number of SPI controllers.
20 - ibm,fsi2spi
24 - description: FSI slave address
26 "#address-cells":
29 "#size-cells":
[all …]
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub
30 clock-names:
38 "#address-cells":
[all …]

123