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/Documentation/devicetree/bindings/mfd/
Dqcom,spmi-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SPMI PMICs multi-function device
11 to the chip via the SPMI (System Power Management Interface) bus.
13 16-bit SPMI peripheral address space into 256 smaller fixed-size regions, 256 bytes
14 each. A function can consume one or more of these fixed-size register regions.
16 The Qualcomm SPMI series includes the PM8941, PM8841, PMA8084, PM8998 and other
17 PMICs. These PMICs use a "QPNP" scheme through SPMI interface.
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Dhisilicon,hi6421-spmi-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/hisilicon,hi6421-spmi-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon 6421v600 SPMI PMIC
10 - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
14 (SPMI) bus. It provides interrupts and power supply.
16 The GPIO and interrupt settings are represented as part of the top-level PMIC
19 The SPMI controller part is provided by
20 Documentation/devicetree/bindings/spmi/hisilicon,hisi-spmi-controller.yaml
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Dti,tps6594.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Julien Panis <jpanis@baylibre.com>
15 PFSM (Pre-configurable Finite State Machine) managing the state of the device.
16 TPS6594 is the super-set device while TPS6593 and LP8764 are derivatives.
21 - ti,lp8764-q1
22 - ti,tps6593-q1
23 - ti,tps6594-q1
24 - ti,tps65224-q1
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/Documentation/devicetree/bindings/clock/
Dqcom,spmi-clkdiv.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SPMI PMIC clock divider
10 - Bjorn Andersson <andersson@kernel.org>
11 - Stephen Boyd <sboyd@kernel.org>
14 Qualcomm SPMI PMIC clock divider configures the clock frequency of a set of
16 functions on GPIO pins.
20 const: qcom,spmi-clkdiv
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/Documentation/devicetree/bindings/iio/adc/
Dqcom,spmi-vadc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm's SPMI PMIC ADC
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 SPMI PMIC voltage ADC (VADC) provides interface to clients to read
15 voltage. The VADC is a 15-bit sigma-delta ADC.
16 SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read
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/Documentation/devicetree/bindings/pinctrl/
Dqcom,pmic-mpp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PMIC Multi-Purpose Pin (MPP) block
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 - items:
20 - enum:
21 - qcom,pm8019-mpp
22 - qcom,pm8226-mpp
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Dqcom,ipq8064-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq8064-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,ipq8064-pinctrl
28 gpio-reserved-ranges: true
31 "-state$":
33 - $ref: "#/$defs/qcom-ipq8064-tlmm-state"
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Dqcom,pmic-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PMIC GPIO block
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 This binding describes the GPIO block(s) found in the 8xxx series of
19 - enum:
20 - qcom,pm2250-gpio
21 - qcom,pm660-gpio
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/Documentation/arch/arm64/
Dacpi_object_usage.rst16 - Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT
18 - Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT
20 - Optional: AGDI, BGRT, CEDT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT,
22 SDEI, SLIT, SPMI, SRAT, STAO, TCPA, TPM2, UEFI, XENV
24 - Not supported: AEST, APMT, BOOT, DBGP, DMAR, ETDT, HPET, IVRS, LPIT,
41 This table describes a non-maskable event, that is used by the platform
68 Optional, not currently supported, with no real use-case for an
83 time as ARM-compatible hardware is available, and the specification
151 UEFI-based; if it is UEFI-based, this table may be supplied. When this
167 the hardware reduced profile, and only 64-bit address fields will
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