Searched full:sram (Results 1 – 25 of 96) sorted by relevance
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| /Documentation/devicetree/bindings/sram/ |
| D | sram.yaml | 4 $id: http://devicetree.org/schemas/sram/sram.yaml#
7 title: Generic on-chip SRAM
15 Each child of the sram node specifies a region of reserved memory. Each
25 pattern: "^sram(@.*)?"
30 - mmio-sram
31 - amlogic,meson-gxbb-sram
32 - arm,juno-sram-ns
38 - rockchip,rk3288-pmu-sram
47 SRAM clock.
58 Should translate from local addresses within the sram to bus addresses.
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| D | allwinner,sun4i-a10-system-control.yaml | 4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
28 - allwinner,sun4i-a10-sram-controller
29 - allwinner,sun50i-a64-sram-controller
62 "^sram@[a-f0-9]+":
63 $ref: /schemas/sram/sram.yaml#
67 "^sram-section?@[a-f0-9]+$":
76 - const: allwinner,sun4i-a10-sram-a3-a4
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| D | qcom,ocmem.yaml | 4 $id: http://devicetree.org/schemas/sram/qcom,ocmem.yaml#
86 "-sram@[0-9a-f]+$":
103 sram@fdd00000 {
120 gmu-sram@0 {
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| /Documentation/devicetree/bindings/crypto/ |
| D | mv_cesa.txt | 9 region. Can also contain an entry for the SRAM attached to the CESA,
12 - reg-names: "regs". Can contain an "sram" entry, but this representation
17 - marvell,crypto-srams: phandle to crypto SRAM definitions
20 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
21 specified the whole SRAM is used (2KB)
31 marvell,crypto-sram-size = <0x600>;
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| D | marvell-cesa.txt | 13 region. Can also contain an entry for the SRAM attached to the CESA,
16 - reg-names: "regs". Can contain an "sram" entry, but this representation
26 - marvell,crypto-srams: phandle to crypto SRAM definitions
29 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
30 specified the whole SRAM is used (2KB)
43 marvell,crypto-sram-size = <0x600>;
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | canaan,k210-sram.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/canaan,k210-sram.yaml#
7 title: Canaan K210 SRAM memory controller
10 The Canaan K210 SRAM memory controller is responsible for the system's 8 MiB
11 of SRAM. The controller is initialised by the bootloader, which configures
20 - canaan,k210-sram
47 compatible = "canaan,k210-sram";
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | amlogic,meson-mx-ao-arc.yaml | 50 sram:
53 phandles to a reserved SRAM region which is used as the memory of
55 AHB SRAM node as per the generic bindings in
56 Documentation/devicetree/bindings/sram/sram.yaml
70 - sram
83 sram = <&ahb_sram_ao_arc>;
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| D | mtk,scp.yaml | 29 Should contain the address ranges for memory regions SRAM, CFG, and,
81 local SCP SRAM address spaces to bus addresses.
93 Each SCP core has own cache memory. The SRAM and L1TCM are shared by
94 cores. The power of cache, SRAM and L1TCM power should be enabled
95 before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
109 description: The base address and size of SRAM.
113 const: sram
177 - const: sram
191 - const: sram
220 reg-names = "sram", "cfg", "l1tcm";
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| D | ingenic,vpu.yaml | 27 - description: sram registers
34 - const: sram
69 <0x132f0000 0x7000>; /* SRAM */
70 reg-names = "aux", "tcsm0", "tcsm1", "sram";
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| D | ti,k3-dsp-rproc.yaml | 77 sram:
84 phandles to one or more reserved on-chip SRAM regions. The regions
85 should be defined as child nodes of the respective SRAM node, and
87 Documentation/devicetree/bindings/sram/sram.yaml
99 - description: Address and Size of the L2 SRAM internal memory region
118 - description: Address and Size of the L2 SRAM internal memory region
134 - description: Address and Size of the L2 SRAM internal memory region
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | mpu.txt | 14 - sram: Phandle to the ocmcram node
17 - pm-sram: Phandles to ocmcram nodes to be used for power management.
20 data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
52 pm-sram = <&pm_sram_code
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| /Documentation/devicetree/bindings/net/ |
| D | allwinner,sun4i-a10-emac.yaml | 29 allwinner,sram:
30 description: Phandle to the device SRAM
34 - description: phandle to SRAM
43 - allwinner,sram
55 allwinner,sram = <&emac_sram 1>;
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| D | marvell-orion-net.txt | 43 - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM.
44 - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM.
46 - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
47 - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
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| /Documentation/devicetree/bindings/clock/ |
| D | hi6220-clock.txt | 28 - hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;
29 the driver need use the sram to pass parameters for frequency change.
44 hisilicon,hi6220-clk-sram = <&sram>;
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| /Documentation/arch/arm/stm32/ |
| D | stm32-dma-mdma-chaining.rst | 29 the system SRAM) for different peripheral. It can access external RAMs but
110 STM32 DMA-MDMA chaining feature then uses a SRAM buffer. STM32MP1 SoCs embed
113 bad with DDR, while they are optimal with SRAM. Hence the SRAM buffer used
124 | DMA_SxM0AR |<=>| | SRAM | |<=>| []-[]...[] |
140 **1. Allocate a SRAM buffer**
142 SRAM device tree node is defined in SoC device tree. You can refer to it in
143 your board device tree to define your SRAM pool.
146 &sram {
147 my_foo_device_dma_pool: dma-sram@0 {
152 Be careful of the start index, in case there are other SRAM consumers.
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| /Documentation/devicetree/bindings/media/ |
| D | cnm,wave521c.yaml | 39 sram:
42 The VPU uses the SRAM to store some of the reference data instead of
60 sram = <&sram>;
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| D | allwinner,sun4i-a10-video-engine.yaml | 49 allwinner,sram:
53 - description: phandle to SRAM
55 description: Phandle to the device SRAM
73 - allwinner,sram
91 allwinner,sram = <&ve_sram 1>;
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| D | allegro,al5e.yaml | 33 - description: The SRAM
38 - const: sram
79 reg-names = "regs", "sram";
96 reg-names = "regs", "sram";
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| /Documentation/devicetree/bindings/bus/ |
| D | allwinner,sun50i-a64-de2.yaml | 33 allwinner,sram:
35 The SRAM that needs to be claimed to access the display engine
40 - description: phandle to SRAM
63 - allwinner,sram
72 allwinner,sram = <&de2_sram 1>;
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| /Documentation/devicetree/bindings/mailbox/ |
| D | fsl,mu.yaml | 110 "^sram@[a-f0-9]+":
111 $ref: /schemas/sram/sram.yaml#
148 "^sram@[a-f0-9]+": false
175 sram@445b1000 {
176 compatible = "mmio-sram";
182 scmi-sram-section@0 {
187 scmi-sram-section@80 {
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| D | mailbox.txt | 41 sram: sram@50000000 {
42 compatible = "mmio-sram";
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| /Documentation/devicetree/bindings/fsi/ |
| D | fsi-master-ast-cf.txt | 19 - aspeed,sram = <phandle>; : Reference to the SRAM node.
34 aspeed,sram = <&sram>;
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| /Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 32 - sram : Phandles for generic sram driver nodes,
35 data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
76 sram = <&pm_sram_code
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| /Documentation/devicetree/bindings/firmware/ |
| D | nvidia,tegra186-bpmp.yaml | 60 predefined and work on top of either sysram, which is an SRAM inside the
62 See ".../sram/sram.yaml" for the bindings for the SRAM case.
153 sram@30000000 {
154 compatible = "nvidia,tegra186-sysram", "mmio-sram";
160 cpu_bpmp_tx: sram@4e000 {
166 cpu_bpmp_rx: sram@4f000 {
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| /Documentation/devicetree/bindings/mtd/ |
| D | microchip,mchp23k256.txt | 1 * MTD SPI driver for Microchip 23K256 (and similar) serial SRAM
12 spi-sram@0 {
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