Searched full:ss (Results 1 – 25 of 72) sorted by relevance
123
| /Documentation/arch/x86/ |
| D | elf_auxvec.rst | 28 stack_t ss;
30 ss.ss_sp = malloc(ss.ss_size);
31 assert(ss.ss_sp);
33 ss.ss_size = getauxval(AT_MINSIGSTKSZ) + SIGSTKSZ;
34 ss.ss_flags = 0;
36 if (sigaltstack(&ss, NULL))
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| /Documentation/devicetree/bindings/usb/ |
| D | ti,hd3ss3220.yaml | 13 HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel
31 SS data bus to the SS capable connector.
36 description: Super Speed (SS) MUX inputs connected to SS capable connector.
40 description: Output of 2:1 MUX connected to Super Speed (SS) data bus.
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| D | nvidia,tegra124-xusb.yaml | 77 - description: shared reset for xusb_{ss,hs,fs,falcon,host}_src.
123 avdd-usb-ss-pll-supply:
126 hvdd-usb-ss-supply:
129 hvdd-usb-ss-pll-e-supply:
152 - hvdd-usb-ss-supply
197 avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
198 hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
199 hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
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| D | nvidia,tegra210-xusb.yaml | 69 - description: shared reset for xusb_{ss,hs,fs,falcon,host}_src.
126 dvdd-usb-ss-pll-supply:
129 hvdd-usb-ss-pll-e-supply:
185 dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
186 hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
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| D | nvidia,tegra-xudc.yaml | 58 - const: ss
84 - const: ss
199 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
202 power-domain-names = "dev", "ss";
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| D | usb-switch.yaml | 40 Super Speed (SS) Output endpoint to the Type-C connector
45 Super Speed (SS) Input endpoint from the Super-Speed PHY
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| D | nxp,ptn36502.yaml | 31 description: Super Speed (SS) Output endpoint to the Type-C connector
35 description: Super Speed (SS) Input endpoint from the Super-Speed PHY
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| D | mediatek,mtk-xhci.yaml | 100 - description: USB3/SS(P) PHY
102 - description: USB3/SS(P) PHY
104 - description: USB3/SS(P) PHY
106 - description: USB3/SS(P) PHY
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| D | snps,dwc3.yaml | 62 SS PHY in P3. But particular cases may differ from that having less
84 - description: USB3/SS PHY
151 description: Set if we enable P3 OK for U2/SS Inactive quirk
235 snps,parkmode-disable-ss-quirk:
334 size that the core can perform. It only applies to SS Bulk,
362 In Host mode, it only applies to SS Bulk, Isochronous, and Interrupt
460 description: Super Speed (SS) data bus.
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| D | onnn,nb7vpq904m.yaml | 32 description: Super Speed (SS) Output endpoint to the Type-C connector
36 description: Super Speed (SS) Input endpoint from the Super-Speed PHY
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| D | dwc3-cavium.txt | 19 refclk-type-ss = "dlmc_ref_clk0";
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| D | mediatek,mtu3.yaml | 89 - description: USB3/SS(P) PHY
91 - description: USB3/SS(P) PHY
93 - description: USB3/SS(P) PHY
95 - description: USB3/SS(P) PHY
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| /Documentation/devicetree/bindings/phy/ |
| D | qcom,ipq806x-usb-phy-ss.yaml | 4 $id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml#
7 title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER
19 const: qcom,ipq806x-usb-phy-ss
69 compatible = "qcom,ipq806x-usb-phy-ss";
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| D | qcom,usb-ss.yaml | 4 $id: http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#
18 - qcom,usb-ss-28nm-phy
70 compatible = "qcom,usb-ss-28nm-phy";
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| D | transmit-amplitude.yaml | 66 - usb-ss
67 - usb-ss+
102 tx-p2p-microvolt-names = "2500base-x", "usb-hs", "usb-ss";
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| D | brcm,stingray-usb-phy.txt | 5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
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| D | qcom-usb-ipq4019-phy.yaml | 7 title: Qualcom IPQ40xx Dakota HS/SS USB PHY
15 - qcom,usb-ss-ipq4019-phy
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| D | nvidia,tegra210-xusb-padctl.yaml | 229 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
241 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
253 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
265 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
277 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
289 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
301 enum: [ pcie-x1, usb3-ss, pcie-x4 ]
337 enum: [ usb3-ss, sata ]
708 nvidia,function = "usb3-ss";
713 nvidia,function = "usb3-ss";
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| D | nvidia,tegra124-xusb-padctl.yaml | 239 enum: [ pcie, usb3-ss ]
251 enum: [ pcie, usb3-ss ]
263 enum: [ pcie, usb3-ss ]
275 enum: [ pcie, usb3-ss ]
287 enum: [ pcie, usb3-ss ]
315 enum: [ sata, usb3-ss ]
581 nvidia,function = "usb3-ss";
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| D | brcm,sr-pcie-phy.txt | 5 - reg: base address and length of the PCIe SS register space
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| /Documentation/ABI/testing/ |
| D | configfs-usb-gadget-sourcesink | 10 isoc_maxpacket 0 - 1023 (fs), 0 - 1024 (hs/ss)
11 isoc_mult 0..2 (hs/ss only)
12 isoc_maxburst 0..15 (ss only)
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| D | configfs-usb-gadget-uac2 | 11 c_hs_bint capture bInterval for HS/SS (1-4: fixed, 0: auto)
26 p_hs_bint playback bInterval for HS/SS (1-4: fixed, 0: auto)
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| /Documentation/devicetree/bindings/spi/ |
| D | renesas,rzv2m-csi.yaml | 42 renesas,csi-no-ss:
45 The CSI Slave Selection (SS) pin won't be used to enable transmission and
60 renesas,csi-no-ss: [ spi-slave ]
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| D | spi-xilinx.yaml | 28 xlnx,num-ss-bits:
52 xlnx,num-ss-bits = <0x1>;
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| /Documentation/devicetree/bindings/arm/ |
| D | qcom-soc.yaml | 54 - qcom,usb-ss-ipq4019-phy
63 - qcom,ipq806x-usb-phy-ss
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