| /Documentation/devicetree/bindings/soc/starfive/ |
| D | starfive,jh7110-syscon.yaml | 4 $id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
7 title: StarFive JH7110 SoC system controller
13 The StarFive JH7110 SoC system controller provides register information such
20 - const: starfive,jh7110-sys-syscon
25 - starfive,jh7110-aon-syscon
26 - starfive,jh7110-stg-syscon
33 $ref: /schemas/clock/starfive,jh7110-pll.yaml#
48 const: starfive,jh7110-sys-syscon
59 const: starfive,jh7110-aon-syscon
72 compatible = "starfive,jh7110-stg-syscon", "syscon";
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| /Documentation/devicetree/bindings/riscv/ |
| D | starfive.yaml | 4 $id: http://devicetree.org/schemas/riscv/starfive.yaml#
7 title: StarFive SoC-based boards
14 StarFive SoC-based boards
24 - starfive,visionfive-v1
25 - const: starfive,jh7100
31 - starfive,visionfive-2-v1.2a
32 - starfive,visionfive-2-v1.3b
33 - const: starfive,jh7110
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| /Documentation/devicetree/bindings/net/ |
| D | starfive,jh7110-dwmac.yaml | 2 # Copyright (C) 2022 StarFive Technology Co., Ltd.
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
8 title: StarFive JH7110 DWMAC glue layer
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
28 - const: starfive,jh7100-dwmac
31 - const: starfive,jh7110-dwmac
34 - const: starfive,jh8100-dwmac
35 - const: starfive,jh7110-dwmac
57 starfive,tx-use-rgmii-clk:
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| /Documentation/devicetree/bindings/hwmon/ |
| D | starfive,jh71x0-temp.yaml | 4 $id: http://devicetree.org/schemas/hwmon/starfive,jh71x0-temp.yaml#
7 title: StarFive JH71x0 Temperature Sensor
13 StarFive Technology Co. JH71x0 embedded temperature sensor
18 - starfive,jh7100-temp
19 - starfive,jh7110-temp
57 #include <dt-bindings/clock/starfive-jh7100.h>
58 #include <dt-bindings/reset/starfive-jh7100.h>
61 compatible = "starfive,jh7100-temp";
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| /Documentation/devicetree/bindings/phy/ |
| D | starfive,jh7110-pcie-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
7 title: StarFive JH7110 PCIe 2.0 PHY
14 const: starfive,jh7110-pcie-phy
22 starfive,sys-syscon:
32 starfive,stg-syscon:
53 compatible = "starfive,jh7110-pcie-phy";
56 starfive,sys-syscon = <&sys_syscon 0x18>;
57 starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
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| D | starfive,jh7110-dphy-tx.yaml | 4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-tx.yaml#
7 title: Starfive SoC MIPI D-PHY Tx Controller
14 The Starfive SoC uses the MIPI DSI D-PHY based on M31 IP to transfer
19 const: starfive,jh7110-dphy-tx
60 compatible = "starfive,jh7110-dphy-tx";
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| D | starfive,jh7110-dphy-rx.yaml | 4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
7 title: StarFive SoC JH7110 MIPI D-PHY Rx Controller
14 StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
19 const: starfive,jh7110-dphy-rx
61 compatible = "starfive,jh7110-dphy-rx";
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| /Documentation/devicetree/bindings/clock/ |
| D | starfive,jh7110-ispcrg.yaml | 4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
14 const: starfive,jh7110-ispcrg
42 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
47 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
68 #include <dt-bindings/clock/starfive,jh7110-crg.h>
69 #include <dt-bindings/power/starfive,jh7110-pmu.h>
70 #include <dt-bindings/reset/starfive,jh7110-crg.h>
73 compatible = "starfive,jh7110-ispcrg";
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| D | starfive,jh7110-voutcrg.yaml | 4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
7 title: StarFive JH7110 Video-Output Clock and Reset Generator
14 const: starfive,jh7110-voutcrg
44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
70 #include <dt-bindings/clock/starfive,jh7110-crg.h>
71 #include <dt-bindings/power/starfive,jh7110-pmu.h>
72 #include <dt-bindings/reset/starfive,jh7110-crg.h>
75 compatible = "starfive,jh7110-voutcrg";
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| D | starfive,jh7100-audclk.yaml | 4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
7 title: StarFive JH7100 Audio Clock Generator
14 const: starfive,jh7100-audclk
34 See <dt-bindings/clock/starfive-jh7100-audio.h> for valid indices.
47 #include <dt-bindings/clock/starfive-jh7100.h>
50 compatible = "starfive,jh7100-audclk";
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| D | starfive,jh7110-stgcrg.yaml | 4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
7 title: StarFive JH7110 System-Top-Group Clock and Reset Generator
14 const: starfive,jh7110-stgcrg
44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
63 #include <dt-bindings/clock/starfive,jh7110-crg.h>
66 compatible = "starfive,jh7110-stgcrg";
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| D | starfive,jh7110-pll.yaml | 4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
7 title: StarFive JH7110 PLL Clock Generator
22 const: starfive,jh7110-pll
31 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
43 compatible = "starfive,jh7110-pll";
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| D | starfive,jh7100-clkgen.yaml | 4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
7 title: StarFive JH7100 Clock Generator
15 const: starfive,jh7100-clkgen
37 See <dt-bindings/clock/starfive-jh7100.h> for valid indices.
51 compatible = "starfive,jh7100-clkgen";
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| D | starfive,jh7110-aoncrg.yaml | 4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
7 title: StarFive JH7110 Always-On Clock and Reset Generator
14 const: starfive,jh7110-aoncrg
71 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
76 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
90 #include <dt-bindings/clock/starfive,jh7110-crg.h>
93 compatible = "starfive,jh7110-aoncrg";
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| /Documentation/devicetree/bindings/watchdog/ |
| D | starfive,jh7100-wdt.yaml | 4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
7 title: StarFive Watchdog for JH7100 and JH7110 SoC
26 - starfive,jh7100-wdt
27 - starfive,jh7110-wdt
30 - starfive,jh8100-wdt
31 - const: starfive,jh7110-wdt
68 - starfive,jh8100-wdt
86 compatible = "starfive,jh7100-wdt";
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| /Documentation/devicetree/bindings/perf/ |
| D | starfive,jh8100-starlink-pmu.yaml | 4 $id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml#
7 title: StarFive JH8100 StarLink PMU
13 StarFive's JH8100 StarLink PMU integrates one or more CPU cores with a
16 counter. StarFive's JH8100 StarLink PMU is accessed via MMIO.
20 const: starfive,jh8100-starlink-pmu
42 compatible = "starfive,jh8100-starlink-pmu";
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| /Documentation/devicetree/bindings/crypto/ |
| D | starfive,jh7110-crypto.yaml | 4 $id: http://devicetree.org/schemas/crypto/starfive,jh7110-crypto.yaml#
7 title: StarFive Cryptographic Module
16 - starfive,jh7110-crypto
17 - starfive,jh8100-crypto
66 const: starfive,jh7110-crypto
76 const: starfive,jh8100-crypto
86 compatible = "starfive,jh7110-crypto";
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| /Documentation/devicetree/bindings/rng/ |
| D | starfive,jh7110-trng.yaml | 4 $id: http://devicetree.org/schemas/rng/starfive,jh7110-trng.yaml#
7 title: StarFive SoC TRNG Module
16 - const: starfive,jh8100-trng
17 - const: starfive,jh7110-trng
18 - const: starfive,jh7110-trng
52 compatible = "starfive,jh7110-trng";
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| /Documentation/devicetree/bindings/cache/ |
| D | starfive,jh8100-starlink-cache.yaml | 4 $id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
7 title: StarFive StarLink Cache Controller
13 StarFive's StarLink Cache Controller manages the L3 cache shared between
26 - starfive,jh8100-starlink-cache
34 - const: starfive,jh8100-starlink-cache
58 compatible = "starfive,jh8100-starlink-cache", "cache";
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| /Documentation/devicetree/bindings/power/ |
| D | starfive,jh7110-pmu.yaml | 4 $id: http://devicetree.org/schemas/power/starfive,jh7110-pmu.yaml#
7 title: StarFive JH7110 Power Management Unit
13 StarFive JH7110 SoC includes support for multiple power domains which can be
19 - starfive,jh7110-pmu
41 compatible = "starfive,jh7110-pmu";
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| /Documentation/devicetree/bindings/sound/ |
| D | snps,designware-i2s.yaml | 20 - starfive,jh7110-i2stx0
21 - starfive,jh7110-i2stx1
22 - starfive,jh7110-i2srx
78 starfive,syscon:
126 const: starfive,jh7110-i2stx0
141 const: starfive,jh7110-i2stx1
156 const: starfive,jh7110-i2srx
167 - starfive,syscon
170 starfive,syscon: false
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| /Documentation/devicetree/bindings/mmc/ |
| D | starfive,jh7110-mmc.yaml | 4 $id: http://devicetree.org/schemas/mmc/starfive,jh7110-mmc.yaml#
7 title: StarFive Designware Mobile Storage Host Controller
10 StarFive uses the Synopsys designware mobile storage host controller
21 const: starfive,jh7110-mmc
39 starfive,sysreg:
64 compatible = "starfive,jh7110-mmc";
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | starfive,jh8100-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml#
7 title: StarFive External Interrupt Controller
10 StarFive SoC JH8100 contain a external interrupt controller. It can be used
19 const: starfive,jh8100-intc
54 compatible = "starfive,jh8100-intc";
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| /Documentation/devicetree/bindings/reset/ |
| D | starfive,jh7100-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml#
7 title: StarFive JH7100 SoC Reset Controller
15 - starfive,jh7100-reset
33 compatible = "starfive,jh7100-reset";
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| /Documentation/devicetree/bindings/usb/ |
| D | starfive,jh7110-usb.yaml | 4 $id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
7 title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
14 const: starfive,jh7110-usb
18 starfive,stg-syscon:
75 - starfive,stg-syscon
87 compatible = "starfive,jh7110-usb";
91 starfive,stg-syscon = <&stg_syscon 0x4>;
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