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/Documentation/devicetree/bindings/remoteproc/
Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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Dti,k3-dsp-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
19 controller, a dedicated local power/sleep controller etc. The DSP processor
20 cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a
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Dti,davinci-rproc.txt4 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
5 is used to offload some of the processor-intensive tasks or algorithms, for
8 The processor cores in the sub-system usually contain additional sub-modules
10 controller, a dedicated local power/sleep controller etc. The DSP processor
15 Each DSP Core sub-system is represented as a single DT node.
18 --------------------
21 - compatible: Should be one of the following,
22 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
24 - reg: Should contain an entry for each value in 'reg-names'.
27 the parent node's '#address-cells' and '#size-cells' values.
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Dti,keystone-rproc.txt5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
15 Each DSP Core sub-system is represented as a single DT node, and should also
17 or optional properties that enable the OS running on the host processor (ARM
18 CorePac) to perform the device management of the remote processor and to
19 communicate with the remote processor.
22 --------------------
25 - compatible: Should be one of the following,
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Dti,k3-r5f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 R5F processor subsystems
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
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Dti,k3-m4f-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-m4f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 M4F processor subsystems
10 - Hari Nagalla <hnagalla@ti.com>
11 - Mathieu Poirier <mathieu.poirier@linaro.org>
17 home automation applications, may use the M4F core as a remote processor
20 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
25 - ti,am64-m4fss
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Dmtk,scp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 This binding provides support for ARM Cortex M4 Co-processor found on some
19 - mediatek,mt8183-scp
20 - mediatek,mt8186-scp
21 - mediatek,mt8188-scp
22 - mediatek,mt8188-scp-dual
23 - mediatek,mt8192-scp
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/Documentation/devicetree/bindings/mailbox/
Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
15 external to the various processor subsystems and is connected on an
21 controller within a processor subsystem, and there can be more than one line
22 going to a specific processor's interrupt controller. The interrupt line
35 lines can also be routed to different processor sub-systems on DRA7xx as they
40 to different processor subsystems over a limited number of common interrupt
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/Documentation/devicetree/bindings/bus/
Domap-ocp2scp.txt1 * OMAP OCP2SCP - ocp interface to scp interface
4 - compatible : Should be "ti,am437x-ocp2scp" for AM437x processor
5 Should be "ti,omap-ocp2scp" for all others
6 - reg : Address and length of the register set for the device
7 - #address-cells, #size-cells : Must be present if the device has sub-nodes
8 - ranges : the child address space are mapped 1:1 onto the parent address space
9 - ti,hwmods : must be "ocp2scp_usb_phy"
11 Sub-nodes:
12 All the devices connected to ocp2scp are described using sub-node to ocp2scp
15 compatible = "ti,omap-ocp2scp";
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/Documentation/userspace-api/media/
Dglossary.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
52 **Digital Signal Processor**
58 **Field-programmable Gate Array**
63 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
72 together make a larger user-facing functional peripheral. For
80 **Inter-Integrated Circuit**
82 A multi-master, multi-slave, packet switched, single-ended,
84 like sub-device hardware components.
86 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
108 **Image Signal Processor**
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/Documentation/devicetree/bindings/clock/
Dqcom,kpss-gcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
10 - Christian Marangi <ansuelsmth@gmail.com>
13 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
15 to the kpss-gcc registers.
20 - enum:
21 - qcom,kpss-gcc-ipq8064
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Dqcom,kpss-acc-v1.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
10 - Christian Marangi <ansuelsmth@gmail.com>
17 clock-controller for enabling the cpu and handling the aux clocks.
21 const: qcom,kpss-acc-v1
25 - description: Base address and size of the register region
26 - description: Optional base address and size of the alias register region
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/Documentation/devicetree/bindings/mfd/
Dzii,rave-sp.txt1 Zodiac Inflight Innovations RAVE Supervisory Processor
3 RAVE Supervisory Processor communicates with SoC over UART. It is
9 - compatible: Should be one of:
10 - "zii,rave-sp-niu"
11 - "zii,rave-sp-mezz"
12 - "zii,rave-sp-esb"
13 - "zii,rave-sp-rdu1"
14 - "zii,rave-sp-rdu2"
16 - current-speed: Should be set to baud rate SP device is using
18 RAVE SP consists of the following sub-devices:
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/Documentation/admin-guide/media/
Dqcom_camss.rst1 .. SPDX-License-Identifier: GPL-2.0
9 ------------
25 ----------------------------------
30 - 2 / 3 CSIPHY modules. They handle the Physical layer of the CSI2 receivers.
32 - 2 / 4 CSID (CSI Decoder) modules. They handle the Protocol and Application
36 - ISPIF (ISP Interface) module. Handles the routing of the data streams from
38 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
48 -----------------------
52 - Input from camera sensor via CSIPHY;
53 - Generation of test input data by the TG in CSID;
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/Documentation/devicetree/bindings/arm/
Darm,coresight-dummy-source.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
19 there would be Coresight source trace components on sub-processor which
20 are connected to AP processor via debug bus. For these devices, a dummy driver
30 - Mike Leach <mike.leach@linaro.org>
31 - Suzuki K Poulose <suzuki.poulose@arm.com>
32 - James Clark <james.clark@linaro.org>
33 - Mao Jinlong <quic_jinlmao@quicinc.com>
[all …]
/Documentation/devicetree/bindings/power/
Dqcom,kpss-acc-v2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2
10 - Christian Marangi <ansuelsmth@gmail.com>
17 power-manager for enabling the cpu.
21 const: qcom,kpss-acc-v2
25 - description: Base address and size of the register region
26 - description: Optional base address and size of the alias register region
[all …]
/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
3 The MSCM IP contains multiple sub modules, this binding describes the second
6 it controls the directed processor interrupts. The module is available in all
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
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/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,padding.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
16 width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
24 - mediatek,mt8188-disp-padding
25 - mediatek,mt8195-mdp3-padding
30 power-domains:
35 - description: Padding's clocks
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/Documentation/devicetree/bindings/mips/brcm/
Dsoc.txt5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
13 BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
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/Documentation/admin-guide/pm/
Dintel_pstate.rst1 .. SPDX-License-Identifier: GPL-2.0
22 Documentation/admin-guide/pm/cpufreq.rst if you have not done that yet.]
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
27 information about that). For this reason, the representation of P-states used
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
43 time the corresponding CPU is taken offline and need to be re-initialized when
47 only way to pass early-configuration-time parameters to it is via the kernel
63 the processor.
66 -----------
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/Documentation/gpu/
Dkomeda-kms.rst1 .. SPDX-License-Identifier: GPL-2.0
7 The drm/komeda driver supports the Arm display processor D71 and later products,
23 -----
30 ------
39 -------------------
41 frame. its output frame can be fed into post image processor for showing it on
47 --------------------------
51 Post image processor (improc)
52 -----------------------------
53 Post image processor adjusts frame data like gamma and color space to fit the
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/Documentation/devicetree/bindings/soc/fsl/
Dfsl,qman-portal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/fsl,qman-portal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Portals are memory mapped interfaces to QMan that allow low-latency, lock-less
14 interaction by software running on processor cores, accelerators and network
20 - const: fsl,qman-portal
21 - items:
22 - enum:
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/Documentation/networking/dsa/
Dbcm_sf2.rst8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
22 fail-over not to lose packets during a MoCA role re-election, as well as out of
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dti,pruss-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI PRU-ICSS Local Interrupt Controller
10 - Suman Anna <s-anna@ti.com>
13 Each PRU-ICSS has a single interrupt controller instance that is common
22 The property "ti,irqs-reserved" is used for denoting the connection
30 through 19) are connected to new sub-modules within the ICSSG instances.
32 This interrupt-controller node should be defined as a child node of the
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/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra194-cbb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
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