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/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
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Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
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Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19 privilege modes per hart; machine mode and supervisor mode.
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/Documentation/arch/x86/x86_64/
Dfred.rst1 .. SPDX-License-Identifier: GPL-2.0
11 privilege level (ring transitions). The FRED architecture was
20 establishes the full supervisor context and that event return
33 The LKGS instruction can be used by 64-bit operating systems that do
46 framework must be implemented to facilitate the event-to-handler
48 once an event is delivered, and employs a two-level dispatch.
50 The first level dispatching is event type based, and the second level
53 Full supervisor/user context
56 FRED event delivery atomically save and restore full supervisor/user
86 event handling, and each stack level should be configured to use a
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/Documentation/arch/riscv/
Duabi.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Linux User ABI
7 ------------------------------------
14 #. Single-letter extensions come first, in canonical order.
17 #. All multi-letter extensions will be separated from other extensions by an
21 single-letter extensions and before any higher-privileged extensions.
29 #. Standard supervisor-level extensions (starting with 'S') will be listed
30 after standard unprivileged extensions. If multiple supervisor-level
33 #. Standard machine-level extensions (starting with 'Zxm') will be listed
34 after any lower-privileged, standard extensions. If multiple machine-level
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/Documentation/devicetree/bindings/riscv/
Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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/Documentation/core-api/
Derrseq.rst13 It's implemented as an unsigned 32-bit value. The low order bits are
28 +--------------------------------------+----+------------------------+
30 +--------------------------------------+----+------------------------+
32 +--------------------------------------+----+------------------------+
54 They're all handing him work to do -- so much he can't keep track of who
60 but he can't keep track of things at that level of detail, all he can
78 struct supervisor {
83 struct supervisor su;
103 errseq_set(&wd.wd_err, -EIO);
115 to do a one-off job for him. He's not really watching the worker
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Ddma-attributes.rst6 defined in linux/dma-mapping.h.
9 ----------------------
19 ----------------------
29 --------------------------
33 such mapping is non-trivial task and consumes very limited resources
47 ----------------------
71 -------------------------
73 By default DMA-mapping subsystem is allowed to assemble the buffer
80 ---------------------------
82 This is a hint to the DMA-mapping subsystem that it's probably not worth
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/Documentation/ABI/testing/
Dsysfs-class-firmware-attributes1 What: /sys/class/firmware-attributes/*/attributes/*/
13 and will accept UTF-8 input.
21 - enumeration: a set of pre-defined valid values
22 - integer: a range of numerical values
23 - string
26 -----------------
27 - ordered-list - a set of ordered list valid values
54 "enumeration"-type specific properties:
59 semi-colon (``;``).
61 "integer"-type specific properties:
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/Documentation/userspace-api/
Dseccomp_filter.rst25 to time-of-check-time-of-use (TOCTOU) attacks that are common in system
65 call will return -1 and set errno to ``EINVAL``.
73 true, ``-EACCES`` will be returned. This requirement ensures that filter
82 The above call returns 0 on success and non-zero on error.
106 task without executing the system call. ``siginfo->si_call_addr``
108 ``siginfo->si_syscall`` and ``siginfo->si_arch`` will indicate which
111 instruction). The return value register will contain an arch-
112 dependent value -- if resuming execution, set it to something
114 it with ``-ENOSYS`` could overwrite some useful information.)
122 Results in the lower 16-bits of the return value being passed
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/Documentation/devicetree/bindings/
Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - acbel,fsg032
35 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
36 - ad,ad7414 # Deprecated, use adi,ad7414
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/Documentation/virt/kvm/
Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
122 -----------------------
139 -----------------
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/Documentation/devicetree/bindings/cpu/
Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/Documentation/admin-guide/
Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
69 Bits in debug_level correspond to a level in
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