Searched full:sync (Results 1 – 25 of 253) sorted by relevance
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,q6dsp-lpass-ports.yaml | 52 qcom,tdm-sync-mode:
57 0 = Short sync bit mode
58 1 = Long sync mode
59 2 = Short sync slot mode
61 qcom,tdm-sync-src:
77 qcom,tdm-invert-sync:
81 TDM Invert the sync
99 width in case of sample bit width is 24TDM Invert the sync.
117 - qcom,tdm-sync-mode
118 - qcom,tdm-sync-src
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| D | nvidia,tegra20-ac97.yaml | 44 nvidia,codec-sync-gpios:
58 - nvidia,codec-sync-gpios
80 nvidia,codec-sync-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | fsl,qe-tsa.yaml | 59 The hardware can use four dedicated pins for Tx clock, Tx sync, Rx
60 clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.
67 - description: Receive sync clock
69 - description: Transmit sync clock
80 fsl,rx-frame-sync-delay-bits:
84 Receive frame sync delay in number of bits.
85 Indicates the delay between the Rx sync and the first bit of the Rx
88 fsl,tx-frame-sync-delay-bits:
92 Transmit frame sync delay in number of bits.
93 Indicates the delay between the Tx sync and the first bit of the Tx
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| D | fsl,cpm1-tsa.yaml | 59 The hardware can use four dedicated pins for Tx clock, Tx sync, Rx
60 clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.
80 fsl,rx-frame-sync-delay-bits:
84 Receive frame sync delay in number of bits.
85 Indicates the delay between the Rx sync and the first bit of the Rx
88 fsl,tx-frame-sync-delay-bits:
92 Transmit frame sync delay in number of bits.
93 Indicates the delay between the Tx sync and the first bit of the Tx
106 Frame sync pulses are sampled with the rising edge of the channel
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| D | fsl,ucc-hdlc.yaml | 43 fsl,rx-sync-clock:
45 description: rx-sync
56 fsl,tx-sync-clock:
58 description: tx-sync
124 fsl,rx-sync-clock = "rsync_pin";
125 fsl,tx-sync-clock = "tsync_pin";
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| /Documentation/driver-api/ |
| D | sync_file.rst | 2 Sync File API Guide
8 sync_file API is, and how drivers can support it. Sync file is the carrier of
23 Sync files allows userspace awareness on buffer sharing synchronization between
26 Sync file was originally added in the Android kernel but current Linux Desktop
32 Sync files can go either to or from userspace. When a sync_file is sent from
44 Creating Sync Files
68 Receiving Sync Files from Userspace
72 of the Sync File to the kernel. The kernel can then retrieve the fences
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| /Documentation/devicetree/bindings/display/tilcdc/ |
| D | panel.txt | 11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
45 sync-edge = <0>;
46 sync-ctrl = <1>;
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| /Documentation/fb/ |
| D | viafb.modes | 15 # Sync Width 3.813 us 0.064 ms
40 # Sync Width 2.032 us 0.080 ms
61 # Sync Width 1.556 us 0.069 ms
82 # Sync Width 1.483 us 0.058 ms
103 # Sync Width 1.221 us 0.048 ms
124 # Sync Width 2.679 us 0.099 ms
145 # Sync Width 2.704 us 100.604 us
166 # Sync Width 2.204 us 0.083 ms
187 # Sync Width 3.200 us 0.106 ms
209 # Sync Width 1.616 us 0.064 ms
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| /Documentation/sound/soc/ |
| D | dai.rst | 51 flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
54 while sync runs at the sample rate. PCM also supports Time Division
61 MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
64 MSB is transmitted on rising edge of FRAME/SYNC.
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| /Documentation/input/devices/ |
| D | walkera0701.rst | 68 SYNC BIN OCT
78 SYNC , BIN1, OCT1, BIN2, OCT2 ... BIN24, OCT24, BIN25, next frame SYNC ..
92 1306 uS SYNC 718 uS 101
98 (Warning, pulses on ACK are inverted by transistor, irq is raised up on sync
105 values can be sampled between sync pulses.
117 After last octal value for nibble 24 and next sync pulse one additional
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| /Documentation/devicetree/bindings/display/panel/ |
| D | panel-timing.yaml | 48 Active Front Sync Back
97 description: Horizontal sync length panel timing
133 description: Vertical sync length panel timing
146 Horizontal sync pulse.
154 Vertical sync pulse.
180 Drive sync on rising or sample sync on falling edge.
182 Use 0 to drive sync on falling edge and
183 sample sync on rising edge of pixel clock.
184 Use 1 to drive sync on rising edge and
185 sample sync on falling edge of pixel clock
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| /Documentation/devicetree/bindings/leds/ |
| D | ti.lm36922.yaml | 57 0 - Will enable all LED sync paths
58 1 - Will enable the LED1 sync
59 2 - Will enable the LED2 sync
60 3 - Will enable the LED3 sync (LM36923 only)
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| /Documentation/devicetree/bindings/iio/imu/ |
| D | adi,adis16475.yaml | 74 adi,sync-mode:
76 Configures the device SYNC pin. The following modes are supported
116 adi,sync-mode:
122 adi,sync-mode:
127 adi,sync-mode: [ clocks ]
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| D | adi,adis16480.yaml | 69 sync: In sync mode, the internal clock is disabled and the frequency
83 - sync
133 clock-names = "sync";
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| /Documentation/devicetree/bindings/gpio/ |
| D | sprd,gpio-eic.yaml | 20 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
39 The EIC-sync is similar with GPIO's input function, which is a synchronized
50 - sprd,sc9860-eic-sync
66 - sprd,ums512-eic-sync
67 - const: sprd,sc9860-eic-sync
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | tvp7002.txt | 19 - sync-on-green-active: Active state of Sync-on-green signal property of the
47 sync-on-green-active = <1>;
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| /Documentation/driver-api/memory-devices/ |
| D | ti-gpmc.rst | 65 2. sync common
96 5. read sync muxed
107 6. read sync non-muxed
144 9. write sync muxed
157 10. write sync non-muxed
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| /Documentation/sound/cards/ |
| D | hdspm.rst | 148 Speed-mode or Slave (Autosync). Also see "Preferred Sync Ref"
155 * Preferred Sync Ref
157 * Name -- "Preferred Sync Reference"
164 Within the Auto-sync-Mode the preferred Sync Source can be
287 * MADI Sync Status
289 * Name -- "MADI Sync Lock Status"
298 * Word Clock Sync Status
316 Sync-Reference is either "WordClock", "MADI" or none.
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| /Documentation/gpu/amdgpu/display/ |
| D | dcn-overview.rst | 67 2. Global sync signals (green): It is a set of synchronization signals composed
73 the Global Sync deserves an extra level of detail described in the next
186 Global Sync
197 These atomic register updates are driven by global sync signals in DCN. In
199 signals page flip and vblank events it is helpful to understand how global sync
202 Global sync consists of three signals, VSTARTUP, VUPDATE, and VREADY. These are
206 The global sync signals always happen during VBlank, are independent from the
218 The below picture illustrates the global sync signals:
225 The following picture shows how global sync allows for a mailbox style of
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| /Documentation/networking/ |
| D | ipvs-sysctl.rst | 232 When sync_period and sync_refresh_period are 0, send sync only
239 new sync message. It can be used to avoid sync messages for the
241 if connection state is not changed since last sync.
244 sync rate. Additionally, retry sync_retries times with period of
250 Defines sync retries with period of sync_refresh_period/8. Useful
251 to protect against loss of sync messages. The range of the
256 Hard limit for queued sync messages that are not sent yet. It
272 sync traffic. Every thread will use single UDP port, thread 0 will
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| /Documentation/core-api/ |
| D | swiotlb.rst | 18 the normal DMA map, unmap, and sync APIs when programming a device to do DMA.
21 freeing, and sync'ing of bounce buffers. Since the DMA attributes are per
43 the Linux kernel DMA layer does "sync" operations to cause the CPU to copy the
68 each segment. swiotlb_tbl_map_single() always does a "sync" operation (i.e., a
74 unmap does a "sync" operation to cause a CPU copy of the data from the bounce
77 swiotlb also provides "sync" APIs that correspond to the dma_sync_*() APIs that
79 device. The swiotlb "sync" APIs cause a CPU copy of the data between the
81 "sync" APIs support doing a partial sync, where only a subset of the bounce
86 The swiotlb map/unmap/sync APIs must operate without blocking, as they are
269 can be used when doing sync operations. This original address is saved in the
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| /Documentation/devicetree/bindings/media/ |
| D | renesas,drif.yaml | 19 | Master |-----SS-------->|SYNC DRIFn (slave) |
26 CLK & SYNC. Each internal channel has its own dedicated resources like
31 The internal channels sharing the CLK & SYNC are tied together by their
111 sync-active:
115 Indicates sync signal polarity, 0/1 for low/high respectively.
163 # | Master |-----SS-------->|SYNC DRIFn (slave) |
220 # | Master |-----SS-------->|SYNC DRIFn (slave) |
264 sync-active = <0>;
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| D | nvidia,tegra-vde.yaml | 59 - const: sync-token
109 interrupts = <0 9 4>, /* Sync token */
112 interrupt-names = "sync-token", "bsev", "sxe";
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad7768-1.yaml | 42 adi,sync-in-gpios:
68 - adi,sync-in-gpios
111 adi,sync-in-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
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| /Documentation/devicetree/bindings/pwm/ |
| D | microchip,corepwm.yaml | 37 microchip,sync-update-mask:
48 Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
79 microchip,sync-update-mask = /bits/ 32 <0>;
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