Searched +full:sysmgr +full:- +full:syscon (Results 1 – 3 of 3) sorted by relevance
| /Documentation/devicetree/bindings/mmc/ |
| D | synopsys-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
33 clock-names:
35 - const: biu
[all …]
|
| /Documentation/devicetree/bindings/net/ |
| D | socfpga-dwmac.txt | 9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
26 phy-mode: The phy mode the ethernet operates in
27 altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
32 - compatible : Should be altr,gmii-to-sgmii-2.0
33 - reg-names : Should be "eth_tse_control_port"
[all …]
|
| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
17 - compatible : Should be "altr,socfpga-l2-ecc"
18 - reg : Address and size for ECC error interrupt clear registers.
19 - interrupts : Should be single bit error interrupt, then double bit error
24 - compatible : Should be "altr,socfpga-ocram-ecc"
25 - reg : Address and size for ECC error interrupt clear registers.
26 - iram : phandle to On-Chip RAM definition.
[all …]
|