Searched +full:system +full:- +full:controller (Results 1 – 25 of 809) sorted by relevance
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| /Documentation/devicetree/bindings/arm/hisilicon/controller/ |
| D | sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon system controller
10 - Wei Xu <xuwei5@hisilicon.com>
13 The Hisilicon system controller is used on many Hisilicon boards, it can be
14 used to assist the slave core startup, reboot the system, etc.
16 There are some variants of the Hisilicon system controller, such as HiP01,
17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | mvebu-system-controller.txt | 1 MVEBU System Controller
2 -----------------------
7 - compatible: one of:
8 - "marvell,orion-system-controller"
9 - "marvell,armada-370-xp-system-controller"
10 - "marvell,armada-375-system-controller"
11 - reg: Should contain system controller registers location and length.
15 system-controller@d0018200 {
16 compatible = "marvell,armada-370-xp-system-controller";
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| D | ap80x-system-controller.txt | 1 Marvell Armada AP80x System Controller
5 7K/8K/931x SoCs. It contains system controllers, which provide several
6 registers giving access to numerous features: clocks, pin-muxing and
8 these system controllers.
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
14 SYSTEM CONTROLLER 0
18 -------
21 The Device Tree node representing the AP806/AP807 system controller
24 - 0: reference clock of CPU cluster 0
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
5 either the chip controller or system controller node. The pins
9 A pin-controller node should contain subnodes representing the pin group
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
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| D | sprd,pinctrl.txt | 1 * Spreadtrum Pin Controller
3 The Spreadtrum pin controller are organized in 3 blocks (types).
8 pad driving level, system control select and so on ("domain pad
11 select 3.0v, then the pin can output 3.0v. "system control" is used
12 to choose one function (like: UART0) for which system, since we
16 of them, so we can not make every Spreadtrum-special configuration
32 Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
33 PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
35 - input-enable
36 - input-disable
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| D | cortina,gemini-pinctrl.txt | 1 Cortina Systems Gemini pin controller
3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
5 controller.
7 The pin controller node must be a subnode of the system controller node.
10 - compatible: "cortina,gemini-pinctrl"
12 Subnodes of the pin controller contain pin control multiplexing set-up
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
19 - skew-delay is supported on the Ethernet pins
20 - drive-strength with 4, 8, 12 or 16 mA as argument is supported for
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| /Documentation/devicetree/bindings/arm/keystone/ |
| D | ti,sci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI controller
10 - Nishanth Menon <nm@ti.com>
15 management of the System on Chip (SoC) system. These include various system
18 An example of such an SoC is K2G, which contains the system control hardware
19 block called Power Management Micro Controller (PMMC). This hardware block is
23 See https://software-dl.ti.com/tisci/esd/latest/index.html for protocol definition.
25 The TI-SCI node describes the Texas Instrument's System Controller entity node.
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| /Documentation/devicetree/bindings/soc/microchip/ |
| D | microchip,mpfs-sys-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
10 - Conor Dooley <conor.dooley@microchip.com>
13 PolarFire SoC devices include a microcontroller acting as the system controller,
17 https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
19 Communication with the system controller is done via a mailbox, of which the client
27 const: microchip,mpfs-sys-controller
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| /Documentation/devicetree/bindings/reset/ |
| D | ti,sci-reset.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI reset controller
10 - Nishanth Menon <nm@ti.com>
13 Some TI SoCs contain a system controller (like the Power Management Micro
14 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
16 between the host processor running an OS and the system controller happens
17 through a protocol called TI System Control Interface (TI-SCI protocol).
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| /Documentation/devicetree/bindings/cache/ |
| D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
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| /Documentation/devicetree/bindings/sram/ |
| D | allwinner,sun4i-a10-system-control.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 System Control
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-edac | 1 What: /sys/devices/system/edac/mc/mc*/reset_counters
3 Contact: linux-edac@vger.kernel.org
4 Description: This write-only control file will zero all the statistical
5 counters for UE and CE errors on the given memory controller.
12 What: /sys/devices/system/edac/mc/mc*/seconds_since_reset
14 Contact: linux-edac@vger.kernel.org
19 What: /sys/devices/system/edac/mc/mc*/mc_name
21 Contact: linux-edac@vger.kernel.org
22 Description: This attribute file displays the type of memory controller
25 What: /sys/devices/system/edac/mc/mc*/size_mb
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| /Documentation/devicetree/bindings/clock/ |
| D | ti,sci-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI clock controller
10 - Nishanth Menon <nm@ti.com>
13 Some TI SoCs contain a system controller (like the Power Management Micro
14 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
16 between the host processor running an OS and the system controller happens
17 through a protocol called TI System Control Interface (TI-SCI protocol).
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| D | arm,syscon-icst.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System Controller ICST Clocks
10 - Linus Walleij <linusw@kernel.org>
16 oscillators to their system controllers.
18 The various ARM system controllers contain logic to serialize and initialize
20 into the system controller. Furthermore, to even be able to alter one of
21 these frequencies, the system controller must first be unlocked by
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| D | imx7ulp-scg-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
15 modules, and Core Mode Controller (CMC)1 blocks
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
28 The System Clock Generation (SCG) is responsible for clock generation
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| /Documentation/admin-guide/cgroup-v1/ |
| D | cpuacct.rst | 2 CPU Accounting Controller
5 The CPU accounting controller is used to group tasks using cgroups and
8 The CPU accounting controller supports multi-hierarchy groups. An accounting
14 # mount -t cgroup -ocpuacct none /sys/fs/cgroup
18 the system. /sys/fs/cgroup/tasks lists the tasks in this cgroup.
21 in the system.
35 CPU time obtained by the cgroup into user and system times. Currently
39 system: Time spent by tasks of the cgroup in kernel mode.
41 user and system are in USER_HZ unit.
43 cpuacct controller uses percpu_counter interface to collect user and
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| /Documentation/devicetree/bindings/power/ |
| D | power-controller.txt | 1 * Generic system power control capability
3 Power-management integrated circuits or miscellaneous hardware components are
4 sometimes able to control the system power. The device driver associated with these
6 it can be used to switch off the system. The corresponding device must have the
7 standard property "system-power-controller" in its device node. This property
8 marks the device as able to control the system power. In order to test if this
15 compatible = "active-semi,act8846";
16 system-power-controller;
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| /Documentation/devicetree/bindings/watchdog/ |
| D | armada-37xx-wdt.txt | 1 * Armada 37xx CPU Watchdog Timer Controller
4 - compatible : must be "marvell,armada-3700-wdt"
5 - reg : base physical address of the controller and length of memory mapped
7 - clocks : the clock feeding the watchdog timer. See clock-bindings.txt
8 - marvell,system-controller : reference to syscon node for the CPU Miscellaneous
13 cpu_misc: system-controller@d000 {
14 compatible = "marvell,armada-3700-cpu-misc", "syscon";
19 compatible = "marvell,armada-3700-wdt";
21 marvell,system-controller = <&cpu_misc>;
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | ti,j721e-system-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/soc/ti/ti,j721e-system-controller.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721e System Controller Registers R/W
12 System controller node represents a register region containing a set
14 represent as any specific type of device. The typical use-case is
15 for some other node's driver, or platform-specific code, to acquire
22 - Kishon Vijay Abraham I <kishon@kernel.org>
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| /Documentation/devicetree/bindings/mfd/ |
| D | syscon.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: System Controller Devices
10 System controller node represents a register region containing a set
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
20 - Lee Jones <lee@kernel.org>
30 - al,alpine-sysfabric-servic
31 - allwinner,sun8i-a83t-system-controller
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| /Documentation/arch/x86/ |
| D | earlyprintk.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Mini-HOWTO for using the earlyprintk=dbgp boot option with a
13 [host/target] <-------> [USB debug key] <-------> [client/console]
18 a) Host/target system needs to have USB debug port capability.
21 the lspci -vvv output::
23 # lspci -vvv
25 …00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 03) (p…
27 …Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisIN…
28 …Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- I…
31 Region 0: Memory at fe227000 (32-bit, non-prefetchable) [size=1K]
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,sci-inta.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
17 which handles the termination of system events to that they can
18 be coherently processed by the host(s) in the system. A maximum
22 +-----------------------------------------+
24 | +--------------+ +------------+ |
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| /Documentation/devicetree/bindings/phy/ |
| D | starfive,jh7110-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-pcie-phy
19 "#phy-cells":
22 starfive,sys-syscon:
23 $ref: /schemas/types.yaml#/definitions/phandle-array
25 - items:
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx93-src.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx93-src.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX93 System Reset Controller
10 - Peng Fan <peng.fan@nxp.com>
13 The System Reset Controller (SRC) is responsible for the generation of
14 all the system reset signals and boot argument latching.
17 - Deals with all global system reset sources from other modules,
18 and generates global system reset.
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| /Documentation/devicetree/bindings/arm/ |
| D | atmel-sysregs.txt | 1 Atmel system registers
4 - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid"
5 - reg : Should contain registers location and length
8 - compatible: Should be "atmel,at91sam9260-pit"
9 - reg: Should contain registers location and length
10 - interrupts: Should contain interrupt for the PIT which is the IRQ line
11 shared across all System Controller members.
14 - compatible: Should be "microchip,sam9x60-pit64b" or
15 "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
16 - reg: Should contain registers location and length
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