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/Documentation/devicetree/bindings/phy/
Drealtek,usb2phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stanley Chang <stanley_chang@realtek.com>
20 The USB architecture includes three XHCI controllers.
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
27 |- usb3phy -- phy#0
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/Documentation/devicetree/bindings/interrupt-controller/
Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
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Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
22 the HLIC, which are routed via the platform-level interrupt controller
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/Documentation/virt/
Dparavirt_ops.rst1 .. SPDX-License-Identifier: GPL-2.0
13 including native machine -- without any hypervisors.
16 corresponding to low-level critical instructions and high-level
18 time by enabling binary patching of the low-level critical operations
21 pv_ops operations are classified into three categories:
23 - simple indirect call
24 These operations correspond to high-level functionality where it is
27 - indirect call which allows optimization with binary patch
28 Usually these operations correspond to low-level critical instructions. They
32 - a set of macros for hand written assembly code
/Documentation/devicetree/bindings/watchdog/
Dlinux,wdt-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/linux,wdt-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-controlled Watchdog
10 - Guenter Roeck <linux@roeck-us.net>
11 - Robert Marko <robert.marko@sartura.hr>
15 const: linux,wdt-gpio
24 - description:
25 Either a high-to-low or a low-to-high transition clears the WDT counter.
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/Documentation/scheduler/
Dsched-stats.rst16 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel
17 release). Some counters make more sense to be per-runqueue; other to be
18 per-domain. Note that domains (and their associated information) will only
21 In version 14 of schedstat, there is at least one level of domain
27 are no architectures which need more than three domain levels. The first
38 Note that any such script will necessarily be version-specific, as the main
43 --------------
50 Next three are schedule() statistics:
62 Next three are statistics describing scheduling latency:
71 -----------------
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Dsched-nice-design.rst6 nice-levels implementation in the new Linux scheduler.
12 scheduler, (otherwise we'd have done it long ago) because nice level
19 rule so that nice +19 level would be _exactly_ 1 jiffy. To better
34 -*----------------------------------*-----> [nice level]
35 -20 | +19
52 right minimal granularity - and this translates to 5% CPU utilization.
53 But the fundamental HZ-sensitive property for nice+19 still remained,
56 too _strong_ :-)
59 within the constraints of HZ and jiffies and their nasty design level
63 about Linux's nice level support was its asymmetry around the origin
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/Documentation/devicetree/bindings/opp/
Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
25 pattern: '^opp-table(-[a-z0-9]+)?$'
27 opp-shared:
36 '^opp(-?[0-9]+)*$':
39 One or more OPP nodes describing voltage-current-frequency combinations.
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/Documentation/usb/
Dfunctionfs.rst12 that kernel level composite functions provide when they are added to
28 For more information about FunctionFS descriptors see :doc:`functionfs-desc`
48 level it would look like this::
51 $ mkdir /dev/ffs-mtp && mount -t functionfs mtp /dev/ffs-mtp
52 $ ( cd /dev/ffs-mtp && mtp-daemon ) &
53 $ mkdir /dev/ffs-hid && mount -t functionfs hid /dev/ffs-hid
54 $ ( cd /dev/ffs-hid && hid-daemon ) &
56 On kernel level the gadget checks ffs_data->dev_name to identify
64 parameter's value is just a one-element list, then the behaviour
84 zero-copy fashion, for instance between IIO and the USB stack.
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/Documentation/hwmon/
Dlm78.rst6 * National Semiconductor LM78 / LM78-J
10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
20 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
28 - Frodo Looijaard <frodol@dds.nl>
29 - Jean Delvare <jdelvare@suse.de>
32 -----------
34 This driver implements support for the National Semiconductor LM78, LM78-J
37 There is almost no difference between the three supported chips. Functionally,
38 the LM78 and LM78-J are exactly identical. The LM79 has one more VID line,
40 From here on, LM7* means either of these three types.
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Dpc87360.rst22 -----------------
25 Chip initialization level:
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
49 hardware monitoring chipsets, not only controlling and monitoring three fans,
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
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/Documentation/power/regulator/
Doverview.rst26 - Regulator
27 - Electronic device that supplies power to other devices.
31 Input Voltage -> Regulator -> Output Voltage
34 - PMIC
35 - Power Management IC. An IC that contains numerous
39 - Consumer
40 - Electronic device that is supplied power by a regulator.
41 Consumers can be classified into two types:-
52 - Power Domain
53 - Electronic circuit that is supplied its input power by the
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/Documentation/ABI/testing/
Dsysfs-driver-wacom4 Contact: linux-bluetooth@vger.kernel.org
14 Contact: linux-input@vger.kernel.org
25 Contact: linux-input@vger.kernel.org
30 button is pressed on the stylus. This luminance level is
31 normally lower than the level when a button is pressed.
35 Contact: linux-input@vger.kernel.org
44 Contact: linux-input@vger.kernel.org
49 24HD) status LEDs is active (0..3). The other three LEDs on the
54 Contact: linux-input@vger.kernel.org
58 and Cintiq 24HD) status LEDs is active (0..3). The other three LEDs on
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/Documentation/devicetree/bindings/ata/
Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawn.guo@linaro.org>
14 with some special extensions at integration level.
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
22 - fsl,imx8qm-ahci
[all …]
/Documentation/devicetree/bindings/gpio/
Dgpio-xra1403.txt1 GPIO Driver for XRA1403 16-BIT GPIO Expander With Reset Input from EXAR
3 The XRA1403 is an 16-bit GPIO expander with an SPI interface. Features available:
4 - Individually programmable inputs:
5 - Internal pull-up resistors
6 - Polarity inversion
7 - Individual interrupt enable
8 - Rising edge and/or Falling edge interrupt
9 - Input filter
10 - Individually programmable outputs
11 - Output Level Control
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/Documentation/core-api/
Dgenericirq.rst7 :Copyright: |copy| 2005-2010: Thomas Gleixner
8 :Copyright: |copy| 2005-2006: Ingo Molnar
29 __do_IRQ() super-handler, which is able to deal with every type of
36 - Level type
38 - Edge type
40 - Simple type
44 - Fast EOI type
46 In the SMP world of the __do_IRQ() super-handler another type was
49 - Per CPU type
51 This split implementation of high-level IRQ handlers allows us to
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/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-dma3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 described in "#dma-cells" property description below, using a three-cell
26 - Amelie Delaunay <amelie.delaunay@foss.st.com>
29 - $ref: /schemas/dma/dma-controller.yaml#
33 const: st,stm32mp25-dma3
42 Should contain all of the per-channel DMA interrupts in ascending order
51 power-domains:
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/Documentation/devicetree/bindings/display/
Dst,stm32mp25-lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
15 LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
18 It is composed of three sub blocks:
19 - LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
21 - LVDS PHY: parallelize the data and drives the LVDS data lanes
[all …]
/Documentation/block/
Dioprio.rst7 -----
12 mq-deadline.
15 ------------------
17 Three generic scheduling classes are implemented for io priorities that
29 IOPRIO_CLASS_BE: This is the best-effort scheduling class, which is the default
33 BE prio level, 7 is the lowest. The mapping between cpu nice level and io
34 nice level is determined as: io_nice = (cpu_nice + 20) / 5.
37 level only get io time when no one else needs the disk. The idle class has no
41 -----
45 # ionice -c<class> -n<level> -p<pid>
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/Documentation/userspace-api/media/cec/
Dcec-intro.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _cec-intro:
19 contraption and is an unholy mix of low and high level messages. Some
33 the `v4l-utils <https://git.linuxtv.org/v4l-utils.git/>`_ package. It
34 provides three tools to handle CEC:
36 - cec-ctl: the Swiss army knife of CEC. Allows you to configure, transmit
39 - cec-compliance: does a CEC compliance test of a remote CEC device to
42 - cec-follower: emulates a CEC follower.
/Documentation/admin-guide/
Dsysfs-rules.rst4 The kernel-exported sysfs exports internal kernel implementation details
11 low-level userspace applications, with a new kernel release, the users
12 of sysfs must follow some rules to use an as-abstract-as-possible way to
21 - Do not use libsysfs
23 offer any abstraction, it exposes all the kernel driver-core
31 - sysfs is always at ``/sys``
38 - devices are only "devices"
39 There is no such thing like class-, bus-, physical devices,
41 just simply a "device". Class-, bus-, physical, ... types are just
47 - devpath (``/devices/pci0000:00/0000:00:1d.1/usb2/2-2/2-2:1.0``)
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/Documentation/devicetree/bindings/usb/
Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
19 - fsl,imx23-usb
[all …]
/Documentation/security/
Dsak.rst15 providing SAK. One is the ALT-SYSRQ-K sequence. You shouldn't use
25 run level 5, the X server will restart. This is what you want to
28 What key sequence should you use? Well, CTRL-ALT-DEL is used to reboot
29 the machine. CTRL-ALT-BACKSPACE is magical to the X server. We'll
30 choose CTRL-ALT-PAUSE.
42 systems which implement C2 level security. This author does not
57 # ls -l /proc/[0-9]*/fd/* | grep console
58 l-wx------ 1 root root 64 Mar 18 00:46 /proc/579/fd/0 -> /dev/console
63 root 579 0.0 0.1 1088 436 ? S 00:43 0:00 gpm -t ps/2
79 Also, one prominent Linux distribution has the following three
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/Documentation/userspace-api/media/v4l/
Dpixfmt-srggb8-pisp-comp.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-pix-fmt-pisp-comp1-rggb:
4 .. _v4l2-pix-fmt-pisp-comp1-grbg:
5 .. _v4l2-pix-fmt-pisp-comp1-gbrg:
6 .. _v4l2-pix-fmt-pisp-comp1-bggr:
7 .. _v4l2-pix-fmt-pisp-comp1-mono:
8 .. _v4l2-pix-fmt-pisp-comp2-rggb:
9 .. _v4l2-pix-fmt-pisp-comp2-grbg:
10 .. _v4l2-pix-fmt-pisp-comp2-gbrg:
11 .. _v4l2-pix-fmt-pisp-comp2-bggr:
[all …]
/Documentation/virt/hyperv/
Doverview.rst1 .. SPDX-License-Identifier: GPL-2.0
6 enlightened guest on Microsoft's Hyper-V hypervisor. Hyper-V
7 consists primarily of a bare-metal hypervisor plus a virtual machine
10 partitions. In this documentation, references to Hyper-V usually
15 Hyper-V runs on x86/x64 and arm64 architectures, and Linux guests
16 are supported on both. The functionality and behavior of Hyper-V is
19 Linux Guest Communication with Hyper-V
20 --------------------------------------
21 Linux guests communicate with Hyper-V in four different ways:
24 some guest actions trap to Hyper-V. Hyper-V emulates the action and
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