Searched full:tile (Results 1 – 12 of 12) sorted by relevance
| /Documentation/devicetree/bindings/arm/ |
| D | arm,vexpress-juno.yaml | 22 The motherboard and each core tile should be described by a separate Device
23 Tree source file, with the tile's description including the motherboard file
33 The root node indicates the CPU SoC on the core tile, and this
35 string shall match the name given in the core tile's technical reference
37 further subvariants are released of the core tile, even more fine-granular
46 in MPCore configuration in a test chip on the core tile. See ARM
52 in a test chip on the core tile. It is intended to evaluate NEON, FPU
58 cores in a MPCore configuration in a test chip on the core tile. See
64 A15 CPU cores in a test chip on the core tile. This is the first test
72 in a test chip on the core tile. See ARM DDI 0503I.
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| D | vexpress-scc.txt | 16 where <model> is the full tile model name (as used
17 in the tile's Technical Reference Manual),
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| /Documentation/gpu/xe/ |
| D | xe_tile.rst | 4 Multi-tile Devices
8 :doc: Multi-tile Design
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| /Documentation/userspace-api/media/v4l/ |
| D | metafmt-pisp-be.rst | 37 Tile parameters
41 a single tile in an image is going to be processed. A single set of tile
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| D | ext-ctrls-codec-stateless.rst | 1697 - Specifies the base 2 logarithm of the width of each tile (where the
1702 - Specifies the base 2 logarithm of the height of each tile (where the
2263 - This value plus 1 specifies the number of tile columns partitioning the picture.
2266 - This value plus 1 specifies the number of tile rows partitioning the picture.
2269 - This value plus 1 specifies the width of the i-th tile column in units of
2273 - This value plus 1 specifies the height of the i-th tile row in units of coding
2367 - Specifies that tile column boundaries and likewise tile row boundaries
3108 Represents a single AV1 tile inside an AV1 Tile Group. Note that MiRowStart,
3111 tile_col. See section 6.10.1 "General tile group OBU semantics" in
3127 - Offset from the OBU data, i.e. where the coded tile data actually starts.
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| D | pixfmt-reserved.rst | 246 - Compressed Macro-tile 8-Bit YUV420 format used by Qualcomm platforms.
256 - Compressed Macro-tile 10-Bit YUV420 format used by Qualcomm platforms.
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| D | pixfmt-yuv-planar.rst | 320 contains half the number of lines of the luma plane. Each tile follows the
379 tiles are identical, even though the tile size differ. The image is formed of
402 Note the tile size is 8bytes multiplied by 128 bytes,
427 Layout of MT2110T Chroma Tile
430 ``V4L2_PIX_FMT_MM21`` frame. A partition is a sub-tile of size 16 x 4. The
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| D | vidioc-queryctrl.rst | 548 - A struct :c:type:`v4l2_ctrl_av1_tile_group_entry`, containing AV1 Tile Group
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| /Documentation/devicetree/bindings/media/ |
| D | nxp,dw100.yaml | 15 and wide angle lenses. It is implemented with a line/tile-cache based
16 architecture. With configurable address mapping look up tables and per tile
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,versatile-fpga-irq.txt | 5 controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
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| /Documentation/userspace-api/ |
| D | dma-buf-alloc-exchange.rst | 130 are stored in 4x4 blocks arranged in row-major ordering, i.e. the first tile in
131 a plane stores pixels (0,0) to (3,3) inclusive, and the second tile in a plane
136 formats in which it stores data about the status of every tile, notably
137 including whether the tile is fully populated with pixel data, or can be
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| /Documentation/gpu/ |
| D | drm-kms.rst | 587 Tile Group Property
591 :doc: Tile group
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