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/Documentation/userspace-api/media/v4l/
Dmetafmt-pisp-be.rst17 The PiSP Back End processes images in tiles, and its configuration requires
30 to be processed and is therefore shared across all the tiles of the image. So
32 across all tiles from the same frame.
40 As the ISP processes images in tiles, each set of tiles parameters describe how
42 parameters consist of 160 bytes of data and to process a batch of tiles several
43 sets of tiles parameters are required.
45 Tiles parameters are passed to the ISP by populating the member of
Dpixfmt-yuv-planar.rst102 - 64x32 tiles
111 - 16x16 tiles
125 - 4x4 tiles
146 - 4x4 tiles
153 - 16x32 / 16x16 tiles tiled low bits
160 - 16x32 / 16x16 tiles raster low bits
324 pixels in 2D 16x16 tiles, and stores tiles linearly in memory.
329 pixels in 2D 64x32 tiles, and stores 2x2 groups of tiles in
333 If the vertical resolution is an odd number of tiles, the last row of
334 tiles is stored in linear order. The layouts of the luma and chroma
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Dext-ctrls-codec-stateless.rst3664 - Specifies the number of tiles across the frame.
3667 - Specifies the number of tiles down the frame.
3702 - If set, means that the tiles are uniformly spaced across the frame. (In
3703 other words, all tiles are the same size except for the ones at the
/Documentation/devicetree/bindings/arm/
Darm,integrator.yaml14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
15 so the system is modular and can host a variety of CPU tiles called
16 "core tiles" and referred to in the device tree as "core modules".
Darm,vexpress-juno.yaml18 The board consist of a motherboard and one or more daughterboards (tiles). The
20 tiles.
130 description: When describing tiles consisting of more than one DCC, its
139 the connection between the motherboard and any tiles. Sometimes the
/Documentation/admin-guide/perf/
Dthunderx2-pmu.rst9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
11 to the total number of channels/tiles.
/Documentation/devicetree/bindings/media/
Draspberrypi,pispbe.yaml16 in tiles and produces images consumable by applications.
/Documentation/ABI/testing/
Dsysfs-driver-hid-picolcd41 tiles get changed and it's not appropriate to expect the application
/Documentation/devicetree/bindings/clock/
Darm,syscon-icst.yaml30 In the core modules and logic tiles, the ICST is a configurable clock fed
/Documentation/gpu/
Ddrm-vm-bind-async.rst209 * @tile_mask: Mask for which tiles to create binds for, 0 == All tiles,
/Documentation/admin-guide/media/
Draspberrypi-pisp-be.rst18 The PiSP Back End ISP processes images in tiles. The handling of image
/Documentation/devicetree/bindings/cache/
Dl2c2x0.yaml179 Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that