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/Documentation/devicetree/bindings/timer/
Dti,timer-dm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
[all …]
Dmediatek,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/mediatek,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
14 CPUX (ARM/ARM64 System Timer), GPT (General Purpose Timer)
15 and SYST (System Timer).
20 - items:
21 - enum:
22 - mediatek,mt6577-timer
[all …]
Drockchip,rk-timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/rockchip,rk-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Timer
10 - Daniel Lezcano <daniel.lezcano@linaro.org>
15 - const: rockchip,rk3288-timer
16 - const: rockchip,rk3399-timer
17 - items:
18 - enum:
[all …]
Dnvidia,tegra-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra timer
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
25 A list of 14 interrupts; one per each timer channels 0 through 13
27 - if:
[all …]
Dallwinner,sun4i-a10-timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Timer
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - enum:
17 - allwinner,sun4i-a10-timer
18 - allwinner,sun8i-a23-timer
[all …]
Dfaraday,fttmr010.txt1 Faraday Technology timer
3 This timer is a generic IP block from Faraday Technology, embedded in the
8 - compatible : Must be one of
10 "cortina,gemini-timer", "faraday,fttmr010"
11 "moxa,moxart-timer", "faraday,fttmr010"
12 "aspeed,ast2400-timer"
13 "aspeed,ast2500-timer"
14 "aspeed,ast2600-timer"
16 - reg : Should contain registers location and length
17 - interrupts : Should contain the three timer interrupts usually with
[all …]
Dnuvoton,npcm7xx-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nuvoton,npcm7xx-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM7xx timer
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
11 - Tomer Maimon <tmaimon77@gmail.com>
16 - nuvoton,wpcm450-timer # for Hermon WPCM450
17 - nuvoton,npcm750-timer # for Poleg NPCM750
18 - nuvoton,npcm845-timer # for Arbel NPCM845
[all …]
Dsnps,dw-apb-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB Timer
10 - Daniel Lezcano <daniel.lezcano@linaro.org>
15 - const: snps,dw-apb-timer
16 - enum:
17 - snps,dw-apb-timer-sp
18 - snps,dw-apb-timer-osc
[all …]
Dnvidia,tegra186-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 timer
10 - Thierry Reding <treding@nvidia.com>
13 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
14 counter. Each NV timer selects its timing reference signal from the 1 MHz
16 programmed to generate one-shot, periodic, or watchdog interrupts.
22 - const: nvidia,tegra186-timer
[all …]
Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM architected timer
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
[all …]
Dcirrus,clps711x-timer.txt1 * Cirrus Logic CLPS711X Timer Counter
4 - compatible: Shall contain "cirrus,ep7209-timer".
5 - reg : Address and length of the register set.
6 - interrupts: The interrupt number of the timer.
7 - clocks : phandle of timer reference clock.
9 Note: Each timer should have an alias correctly numbered in "aliases" node.
17 timer1: timer@80000300 {
18 compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
24 timer2: timer@80000340 {
25 compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
Dcirrus,ep9301-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/cirrus,ep9301-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic EP93xx timer
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
16 - const: cirrus,ep9301-timer
17 - items:
18 - enum:
[all …]
Dlsi,zevio-timer.txt1 TI-NSPIRE timer
5 - compatible : should be "lsi,zevio-timer".
6 - reg : The physical base address and size of the timer (always first).
7 - clocks: phandle to the source clock.
11 - interrupts : The interrupt number of the first timer.
12 - reg : The interrupt acknowledgement registers
13 (always after timer base address)
15 If any of the optional properties are not given, the timer is added as a
16 clock-source only.
20 timer {
[all …]
Darm,twd-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Timer
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-timer
[all …]
Dbrcm,bcm2835-system-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/brcm,bcm2835-system-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2835 System Timer
10 - Stefan Wahren <wahrenst@gmx.net>
11 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
14 The System Timer peripheral provides four 32-bit timer channels and a
15 single 64-bit free running counter. Each channel has an output compare
21 const: brcm,bcm2835-system-timer
[all …]
Dmarvell,armada-370-xp-timer.txt2 ---------------------------------------
5 - compatible: Should be one of the following
6 "marvell,armada-370-timer",
7 "marvell,armada-375-timer",
8 "marvell,armada-xp-timer".
9 - interrupts: Should contain the list of Global Timer interrupts and
10 then local timer interrupts
11 - reg: Should contain location and length for timers register. First
12 pair for the Global Timer registers, second pair for the
15 Clocks required for compatible = "marvell,armada-370-timer":
[all …]
Dti,keystone-timer.txt1 * Device tree bindings for Texas instruments Keystone timer
3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 It is global timer is a free running up-counter and can generate interrupt
17 - compatible : should be "ti,keystone-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupt generated by the timer.
20 - clocks : the clock feeding the timer clock.
24 timer@22f0000 {
[all …]
Darm,mps2-timer.txt1 ARM MPS2 timer
3 The MPS2 platform has simple general-purpose 32 bits timers.
6 - compatible : Should be "arm,mps2-timer"
7 - reg : Address and length of the register set
8 - interrupts : Reference to the timer interrupt
11 - clocks : The input clock of the timer
12 - clock-frequency : The rate in HZ in input of the ARM MPS2 timer
16 timer1: mps2-timer@40000000 {
17 compatible = "arm,mps2-timer";
23 timer2: mps2-timer@40001000 {
[all …]
Dxlnx,xps-timer.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx LogiCORE IP AXI Timer
10 - Sean Anderson <sean.anderson@seco.com>
15 const: xlnx,xps-timer-1.00.a
20 clock-names:
29 '#pwm-cells': true
31 xlnx,count-width:
[all …]
Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
[all …]
Dst,spear-timer.txt1 * SPEAr ARM Timer
3 ** Timer node required properties:
5 - compatible : Should be:
6 "st,spear-timer"
7 - reg: Address range of the timer registers
8 - interrupt: Should contain the timer interrupt number
12 timer@f0000000 {
13 compatible = "st,spear-timer";
/Documentation/sound/
Dutimers.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Userspace-driven timers
12 This document describes the userspace-driven timers: virtual ALSA timers
15 stream with timer sources which we don't have ALSA timers exported for
17 two virtual sound devices using ``snd-aloop`` (for instance, when
18 we have a network application sending frames to one snd-aloop device,
19 and another sound application listening on the other end of snd-aloop).
21 Enabling userspace-driven timers
24 The userspace-driven timers could be enabled in the kernel using the
28 Userspace-driven timers API
[all …]
/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic-timer.txt4 - compatible: "fsl,mpic-global-timer"
6 - reg : Contains two regions. The first is the main timer register bank
7 (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
10 - fsl,available-ranges: use <start count> style section to define which
11 timer interrupts can be used. This property is optional; without this,
14 - interrupts: one interrupt per timer in the group, in order, starting
15 with timer zero. If timer-available-ranges is present, only the
19 /* Note that this requires #interrupt-cells to be 4 */
20 timer0: timer@41100 {
21 compatible = "fsl,mpic-global-timer";
[all …]
/Documentation/leds/
Dledtrig-transient.rst5 The leds timer trigger does not currently have an interface to activate
6 a one shot timer. The current support allows for setting two timers, one for
15 Without one shot timer interface, user space can still use timer trigger to
16 set a timer to hold a state, however when user space application crashes or
17 goes away without deactivating the timer, the hardware will be left in that
20 Transient trigger addresses the need for one shot timer activation. The
54 deactivation routine, will cancel any timer that is active before it cleans
56 non-transient state. When driver gets suspended, irrespective of the transient
71 - duration allows setting timer value in msecs. The initial value is 0.
72 - activate allows activating and deactivating the timer specified by
[all …]
/Documentation/devicetree/bindings/soc/microchip/
Datmel,at91rm9200-tcb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel Timer Counter Block
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
14 timer has three channels with two counters each.
19 - enum:
20 - atmel,at91rm9200-tcb
[all …]

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