| /Documentation/devicetree/bindings/timer/ |
| D | ti,timer-dm.yaml | 4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
7 title: TI dual-mode timer
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
20 - ti,am335x-timer
21 - ti,am335x-timer-1ms
22 - ti,am654-timer
23 - ti,dm814-timer
24 - ti,dm816-timer
25 - ti,omap2420-timer
26 - ti,omap3430-timer
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| D | mediatek,timer.yaml | 4 $id: http://devicetree.org/schemas/timer/mediatek,timer.yaml#
14 CPUX (ARM/ARM64 System Timer), GPT (General Purpose Timer)
15 and SYST (System Timer).
22 - mediatek,mt6577-timer
23 - mediatek,mt6765-timer
28 - mediatek,mt2701-timer
29 - mediatek,mt6580-timer
30 - mediatek,mt6582-timer
31 - mediatek,mt6589-timer
32 - mediatek,mt7623-timer
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| D | rockchip,rk-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/rockchip,rk-timer.yaml#
7 title: Rockchip Timer
15 - const: rockchip,rk3288-timer
16 - const: rockchip,rk3399-timer
19 - rockchip,rv1108-timer
20 - rockchip,rv1126-timer
21 - rockchip,rk3036-timer
22 - rockchip,rk3128-timer
23 - rockchip,rk3188-timer
24 - rockchip,rk3228-timer
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| D | nvidia,tegra-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
7 title: NVIDIA Tegra timer
17 const: nvidia,tegra210-timer
25 A list of 14 interrupts; one per each timer channels 0 through 13
33 - nvidia,tegra114-timer
34 - nvidia,tegra124-timer
35 - nvidia,tegra132-timer
36 - const: nvidia,tegra30-timer
38 - const: nvidia,tegra30-timer
39 - const: nvidia,tegra20-timer
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| D | allwinner,sun4i-a10-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml#
7 title: Allwinner A10 Timer
17 - allwinner,sun4i-a10-timer
18 - allwinner,sun8i-a23-timer
19 - allwinner,sun8i-v3s-timer
20 - allwinner,suniv-f1c100s-timer
23 - allwinner,sun20i-d1-timer
24 - allwinner,sun50i-a64-timer
25 - allwinner,sun50i-h6-timer
26 - allwinner,sun50i-h616-timer
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| D | faraday,fttmr010.txt | 1 Faraday Technology timer
3 This timer is a generic IP block from Faraday Technology, embedded in the
10 "cortina,gemini-timer", "faraday,fttmr010"
11 "moxa,moxart-timer", "faraday,fttmr010"
12 "aspeed,ast2400-timer"
13 "aspeed,ast2500-timer"
14 "aspeed,ast2600-timer"
17 - interrupts : Should contain the three timer interrupts usually with
23 - clock-names : should be "EXTCLK" and "PCLK" for the external tick timer
26 type is "cortina,gemini-timer"
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| D | nuvoton,npcm7xx-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/nuvoton,npcm7xx-timer.yaml#
7 title: Nuvoton NPCM7xx timer
16 - nuvoton,wpcm450-timer # for Hermon WPCM450
17 - nuvoton,npcm750-timer # for Poleg NPCM750
18 - nuvoton,npcm845-timer # for Arbel NPCM845
25 - description: The timer interrupt of timer 0
29 - description: The reference clock for timer 0
30 - description: The reference clock for timer 1
31 - description: The reference clock for timer 2
32 - description: The reference clock for timer 3
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| D | snps,dw-apb-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml#
7 title: Synopsys DesignWare APB Timer
15 - const: snps,dw-apb-timer
17 - snps,dw-apb-timer-sp
18 - snps,dw-apb-timer-osc
33 - description: Timer ticks reference clock source
39 - const: timer
62 timer@ffe00000 {
63 compatible = "snps,dw-apb-timer";
67 clock-names = "timer", "pclk";
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| D | nvidia,tegra186-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
7 title: NVIDIA Tegra186 timer
13 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
14 counter. Each NV timer selects its timing reference signal from the 1 MHz
22 - const: nvidia,tegra186-timer
24 The Tegra186 timer provides ten 29-bit timer counters.
25 - const: nvidia,tegra234-timer
27 The Tegra234 timer provides sixteen 29-bit timer counters.
39 const: nvidia,tegra186-timer
45 One per each timer channels 0 through 9.
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| D | arm,arch_timer.yaml | 4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
7 title: ARM architected timer
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
15 physical and optional virtual timer per frame.
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
25 - const: arm,cortex-a15-timer
26 - const: arm,armv7-timer
29 - arm,armv7-timer
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| D | cirrus,clps711x-timer.txt | 1 * Cirrus Logic CLPS711X Timer Counter
4 - compatible: Shall contain "cirrus,ep7209-timer".
6 - interrupts: The interrupt number of the timer.
7 - clocks : phandle of timer reference clock.
9 Note: Each timer should have an alias correctly numbered in "aliases" node.
17 timer1: timer@80000300 {
18 compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
24 timer2: timer@80000340 {
25 compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
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| D | cirrus,ep9301-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/cirrus,ep9301-timer.yaml#
7 title: Cirrus Logic EP93xx timer
16 - const: cirrus,ep9301-timer
19 - cirrus,ep9302-timer
20 - cirrus,ep9307-timer
21 - cirrus,ep9312-timer
22 - cirrus,ep9315-timer
23 - const: cirrus,ep9301-timer
43 timer@80810000 {
44 compatible = "cirrus,ep9301-timer";
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| D | lsi,zevio-timer.txt | 1 TI-NSPIRE timer
5 - compatible : should be "lsi,zevio-timer".
6 - reg : The physical base address and size of the timer (always first).
11 - interrupts : The interrupt number of the first timer.
13 (always after timer base address)
15 If any of the optional properties are not given, the timer is added as a
20 timer {
21 compatible = "lsi,zevio-timer";
29 timer {
30 compatible = "lsi,zevio-timer";
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| D | brcm,bcm2835-system-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/brcm,bcm2835-system-timer.yaml#
7 title: BCM2835 System Timer
14 The System Timer peripheral provides four 32-bit timer channels and a
21 const: brcm,bcm2835-system-timer
28 - description: System Timer Compare 0 match (used by VideoCore GPU)
29 - description: System Timer Compare 1 match (usable for ARM core)
30 - description: System Timer Compare 2 match (used by VideoCore GPU)
31 - description: System Timer Compare 3 match (usable for ARM core)
44 timer@7e003000 {
45 compatible = "brcm,bcm2835-system-timer";
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| D | arm,twd-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
7 title: ARM Timer-Watchdog Timer
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
23 - arm,cortex-a9-twd-timer
24 - arm,cortex-a5-twd-timer
25 - arm,arm11mp-twd-timer
38 If present, the timer is powered through an always-on power domain,
52 timer@2c000600 {
53 compatible = "arm,arm11mp-twd-timer";
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| D | marvell,armada-370-xp-timer.txt | 6 "marvell,armada-370-timer",
7 "marvell,armada-375-timer",
8 "marvell,armada-xp-timer".
9 - interrupts: Should contain the list of Global Timer interrupts and
10 then local timer interrupts
12 pair for the Global Timer registers, second pair for the
15 Clocks required for compatible = "marvell,armada-370-timer":
18 Clocks required for compatibles = "marvell,armada-xp-timer",
19 "marvell,armada-375-timer":
29 timer {
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| D | ti,keystone-timer.txt | 1 * Device tree bindings for Texas instruments Keystone timer
3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 It is global timer is a free running up-counter and can generate interrupt
17 - compatible : should be "ti,keystone-timer".
19 - interrupts : interrupt generated by the timer.
20 - clocks : the clock feeding the timer clock.
24 timer@22f0000 {
25 compatible = "ti,keystone-timer";
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| D | arm,mps2-timer.txt | 1 ARM MPS2 timer
6 - compatible : Should be "arm,mps2-timer"
8 - interrupts : Reference to the timer interrupt
11 - clocks : The input clock of the timer
12 - clock-frequency : The rate in HZ in input of the ARM MPS2 timer
16 timer1: mps2-timer@40000000 {
17 compatible = "arm,mps2-timer";
23 timer2: mps2-timer@40001000 {
24 compatible = "arm,mps2-timer";
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| D | xlnx,xps-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
7 title: Xilinx LogiCORE IP AXI Timer
15 const: xlnx,xps-timer-1.00.a
38 xlnx,one-timer-only:
42 Whether only one timer is present in this block.
47 - xlnx,one-timer-only
58 xlnx,one-timer-only:
74 timer@800e0000 {
77 compatible = "xlnx,xps-timer-1.00.a";
81 xlnx,one-timer-only = <0x0>;
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| D | riscv,timer.yaml | 4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
7 title: RISC-V timer
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
15 timer interrupts of this device are configured using the RISC-V SBI Time
18 The clock frequency of RISC-V timer device is specified via the
25 - riscv,timer
31 riscv,timer-cannot-wake-cpu:
34 If present, the timer interrupt cannot wake up the CPU from one or
45 timer {
46 compatible = "riscv,timer";
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| D | st,spear-timer.txt | 1 * SPEAr ARM Timer
3 ** Timer node required properties:
6 "st,spear-timer"
7 - reg: Address range of the timer registers
8 - interrupt: Should contain the timer interrupt number
12 timer@f0000000 {
13 compatible = "st,spear-timer";
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| /Documentation/sound/ |
| D | utimers.rst | 15 stream with timer sources which we don't have ALSA timers exported for
31 Userspace application can create a userspace-driven ALSA timer by
33 ``/dev/snd/timer`` device file descriptor. The ``snd_timer_uinfo``
46 the virtual timer. ``resolution`` field simply provides an information
47 about the virtual timer, but does not affect the timing itself. ``id``
49 field after the call can be used as a timer subdevice number when
50 passing the timer to ``snd-aloop`` kernel module or other userspace
55 a timer file descriptor, which can be used to trigger the timer, in the
57 descriptor for the timer guarantees that the timer can only be triggered
58 by the process which created it. The timer then can be triggered with
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-platform-ACPI-TAD | 16 BIT(5): The AC timer wakes up from S4 if set
17 BIT(6): The AC timer wakes up from S5 if set
18 BIT(7): The DC timer wakes up from S4 if set
19 BIT(8): The DC timer wakes up from S5 if set
28 (RW) The AC alarm timer value.
30 Reads return the current AC alarm timer value in seconds or
33 Write a new AC alarm timer value in seconds or "disabled" to it
34 to set the AC alarm timer or to disable it, respectively.
36 If the AC alarm timer is set through this attribute and it
45 (RW) The AC alarm expired timer wake policy (see ACPI 6.2,
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-timer.txt | 4 - compatible: "fsl,mpic-global-timer"
6 - reg : Contains two regions. The first is the main timer register bank
7 (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
11 timer interrupts can be used. This property is optional; without this,
14 - interrupts: one interrupt per timer in the group, in order, starting
15 with timer zero. If timer-available-ranges is present, only the
20 timer0: timer@41100 {
21 compatible = "fsl,mpic-global-timer";
31 timer1: timer@42100 {
32 compatible = "fsl,mpic-global-timer";
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| /Documentation/leds/ |
| D | ledtrig-transient.rst | 5 The leds timer trigger does not currently have an interface to activate
6 a one shot timer. The current support allows for setting two timers, one for
15 Without one shot timer interface, user space can still use timer trigger to
16 set a timer to hold a state, however when user space application crashes or
17 goes away without deactivating the timer, the hardware will be left in that
20 Transient trigger addresses the need for one shot timer activation. The
54 deactivation routine, will cancel any timer that is active before it cleans
71 - duration allows setting timer value in msecs. The initial value is 0.
72 - activate allows activating and deactivating the timer specified by
79 - one shot timer activate mechanism.
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