Searched +full:top +full:- +full:level (Results 1 – 25 of 280) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | pistachio-clock.txt | 5 general control, and top general control) which are instantiated individually
6 from the device-tree.
9 ----------------
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
21 co-processor), audio, and several peripherals.
24 - compatible: Must be "img,pistachio-clk".
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| D | google,gs101-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Griffin <peter.griffin@linaro.org>
16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
25 'dt-bindings/clock/gs101.h' header.
30 - google,gs101-cmu-top
31 - google,gs101-cmu-apm
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| D | samsung,exynosautov920-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sunyeal Hong <sunyeal.hong@samsung.com>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
20 The external OSCCLK must be defined as fixed-rate clock in dts.
22 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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| D | samsung,exynos7885-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dávid Virág <virag.david003@gmail.com>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
21 as a fixed-rate clock in dts.
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| /Documentation/devicetree/bindings/sound/ |
| D | img,pistachio-internal-dac.txt | 5 - compatible: "img,pistachio-internal-dac"
7 - img,cr-top : Must contain a phandle to the top level control syscon
10 - VDD-supply : Digital power supply regulator (+1.8V or +3.3V)
14 internal_dac: internal-dac {
15 compatible = "img,pistachio-internal-dac";
16 img,cr-top = <&cr_top>;
17 VDD-supply = <&supply3v3>;
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| /Documentation/driver-api/media/drivers/ |
| D | pvrusb2.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 ----------
13 Its history started with the reverse-engineering effort by Björn
29 1. Low level wire-protocol implementation with the device.
34 3. High level hardware driver implementation which coordinates all
38 tear-down, arbitration, and interaction with high level
42 5. High level interfaces which glue the driver to various published
45 The most important shearing layer is between the top 2 layers. A
47 conceivable API can be laid on top of the core driver. (Yes, the
54 right now the V4L high level interface is the most complete, the
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| /Documentation/sphinx/ |
| D | parallel-wrapper.sh | 2 # SPDX-License-Identifier: GPL-2.0+
5 # environment (as exported by scripts/jobserver-exec), or fall back to
6 # the "auto" parallelism when "-jN" is not specified at the top-level
13 if [ -z "$parallel" ] ; then
14 # If no parallelism is specified at the top-level make, then
15 # fall back to the expected "-jauto" mode that the "htmldocs"
17 auto=$(perl -e 'open IN,"'"$sphinx"' --version 2>&1 |";
24 if [ -n "$auto" ] ; then
28 # Only if some parallelism has been determined do we add the -jN option.
29 if [ -n "$parallel" ] ; then
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,mpic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
14 platforms it also provides inter-processor interrupts.
26 - description: main registers
27 - description: per-cpu registers
31 - description: |
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| D | brcm,bcm2835-armctrl-ic.txt | 1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
9 interrupts, but the per-CPU interrupt controller is the root, and an
14 - compatible : should be "brcm,bcm2835-armctrl-ic" or
15 "brcm,bcm2836-armctrl-ic"
16 - reg : Specifies base physical address and size of the registers.
17 - interrupt-controller : Identifies the node as an interrupt controller
18 - #interrupt-cells : Specifies the number of cells needed to encode an
28 Additional required properties for brcm,bcm2836-armctrl-ic:
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| D | brcm,bcm7038-l1-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7038-style Level 1 interrupt controller
10 This block is a first level interrupt controller that is typically connected
11 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
16 - 64, 96, 128, or 160 incoming level IRQ lines
18 - Most onchip peripherals are wired directly to an L1 input
20 - A separate instance of the register set for each CPU, allowing individual
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| D | abilis,tb10x-ictl.txt | 1 TB10x Top Level Interrupt Controller
5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
16 - interrupts: Specifies the list of interrupt lines which are handled by
18 are mapped one-to-one to parent interrupts.
21 -------
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| /Documentation/admin-guide/cifs/ |
| D | winucase_convert.pl | 1 #!/usr/bin/perl -w
3 # winucase_convert.pl -- convert "Windows 8 Upper Case Mapping Table.txt" to
4 # a two-level set of C arrays.
28 $top[$firstchar][$secondchar] = $uppercase;
32 next if (!$top[$i]);
41 printf("0x%4.4x,", $top[$i][$j] ? $top[$i][$j] : 0);
50 } elsif ($top[$i]) {
56 if ($top[$i]) {
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| /Documentation/devicetree/bindings/display/msm/ |
| D | dsi-phy-10nm.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-10nm
19 - qcom,dsi-phy-10nm-8998
23 - description: dsi phy register set
24 - description: dsi phy lane register set
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | qcom,tlmm-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,tlmm-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Top Level Mode Multiplexer (TLMM) definitions
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 This defines the common properties used to describe all Qualcomm Top Level
23 interrupt-controller: true
25 '#interrupt-cells':
28 include/dt-bindings/interrupt-controller/irq.h
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| /Documentation/devicetree/bindings/ |
| D | jailhouse.txt | 1 Jailhouse non-root cell device tree bindings
2 --------------------------------------------
4 When running in a non-root Jailhouse cell (partition), the device tree of this
5 platform shall have a top-level "hypervisor" node with the following
8 - compatible = "jailhouse,cell"
|
| D | writing-schema.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 Writing Devicetree Bindings in json-schema
6 Devicetree bindings are written using json-schema vocabulary. Schema files are
7 written in a JSON-compatible subset of YAML. YAML is used instead of JSON as it
11 Also see :ref:`example-schema`.
14 ---------------
16 Each schema doc is a structured json-schema which is defined by a set of
17 top-level properties. Generally, there is one binding defined per file. The
18 top-level json-schema properties used are:
21 A json-schema unique identifier string. The string must be a valid
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| /Documentation/arch/powerpc/ |
| D | imc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 IMC (In-Memory Collection Counters)
17 IMC (In-Memory collection counters) is a hardware monitoring facility that
18 collects large numbers of hardware performance events at Nest level (these are
19 on-chip but off-core), Core level and Thread level.
22 (On-Chip Controller) complex. The microcode collects the counter data and moves
25 The Core and Thread IMC PMU counters are handled in the core. Core level PMU
26 counters give us the IMC counters' data per core and thread level PMU counters
33 - Event name
34 - Event Offset
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| /Documentation/driver-api/fpga/ |
| D | intro.rst | 16 other users. Write the linux-fpga mailing list and maintainers and
24 ------------
27 this is the subsystem for you. Low level FPGA manager drivers contain
29 includes the framework in fpga-mgr.c and the low level drivers that
33 -----------
37 programming begins and re-enabled afterwards. An FPGA bridge may be
40 of an FPGA. This subsystem includes fpga-bridge.c and the low level
44 -----------
46 If you are adding a new interface to the FPGA framework, add it on top
49 The FPGA Region framework (fpga-region.c) associates managers and
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| /Documentation/devicetree/bindings/fsi/ |
| D | fsi.txt | 4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
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| /Documentation/arch/x86/ |
| D | pti.rst | 1 .. SPDX-License-Identifier: GPL-2.0
27 This approach helps to ensure that side-channel attacks leveraging
30 time. Once enabled at compile-time, it can be disabled at boot with
31 the 'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt).
42 crippled by setting the NX bit in the top level. This ensures
43 that any missed kernel->user CR3 switch will immediately crash
49 each CPU's copy of the area a compile-time-fixed virtual address.
53 makes entries in the top (PGD) level. In addition to setting the
57 This sharing at the PGD level also inherently shares all the lower
65 Protection against side-channel attacks is important. But,
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| /Documentation/admin-guide/mm/ |
| D | concepts.rst | 7 systems from MMU-less microcontrollers to supercomputers. The memory
52 The tables at the lowest level of the hierarchy contain physical
55 levels. The pointer to the top level page table resides in a
57 register to access the top level page table. The high bits of the
58 virtual address are used to index an entry in the top level page
59 table. That entry is then used to access the next level in the
61 that level page table. The lowest bits in the virtual address define
78 and the third level page tables. In Linux such pages are called
80 improves TLB hit-rate and thus improves overall system performance.
87 Documentation/admin-guide/mm/hugetlbpage.rst.
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| /Documentation/ABI/testing/ |
| D | sysfs-class-led | 9 just be turned on for non-zero brightness settings.
23 Documentation/leds/leds-class-multicolor.rst.
30 Writing non-zero to this file while trigger is active changes the
31 top brightness trigger is going to use.
40 Maximum brightness level for this LED, default is 255 (LED_FULL).
49 Last hardware set brightness level for this LED. Some LEDs
57 Reading this file will return the last brightness level set
73 their documentation see `sysfs-class-led-trigger-*`.
|
| /Documentation/arch/x86/x86_64/ |
| D | mm.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Complete virtual memory map with 4-level page tables
12 - Negative addresses such as "-23 TB" are absolute addresses in bytes, counted down
13 from the top of the 64-bit address space. It's easier to understand the layout
14 when seen both in absolute addresses and in distance-from-top notation.
16 For example 0xffffe90000000000 == -23 TB, it's 23 TB lower than the top of the
17 64-bit address space (ffffffffffffffff).
19 Note that as we get closer to the top of the address space, the notation changes
22 - "16M TB" might look weird at first sight, but it's an easier way to visualize size
24 It also shows it nicely how incredibly large 64-bit address space is.
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,video.txt | 2 -------------------------------
5 ---------------
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
10 node of the VIPP represents as a top level node of the pipeline and defines
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
26 - direction: should be either "input" or "output" depending on the direction
34 dma-names = "port0", "port1";
37 #address-cells = <1>;
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx8mq-vpu-blk-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ VPU blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to
20 - const: fsl,imx8mq-vpu-blk-ctrl
25 '#power-domain-cells':
28 power-domains:
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