| /Documentation/devicetree/bindings/clock/ |
| D | mediatek,topckgen.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#
14 The Mediatek topckgen controller provides various clocks to the system.
21 - mediatek,mt6797-topckgen
22 - mediatek,mt7622-topckgen
23 - mediatek,mt8135-topckgen
24 - mediatek,mt8173-topckgen
25 - mediatek,mt8516-topckgen
27 - const: mediatek,mt7623-topckgen
28 - const: mediatek,mt2701-topckgen
32 - mediatek,mt2701-topckgen
[all …]
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| D | mediatek,mt8365-sys-clock.yaml | 14 The topckgen provides dividers and muxes which provides the clock source to other IP blocks.
21 - mediatek,mt8365-topckgen
43 topckgen: clock-controller@10000000 {
44 compatible = "mediatek,mt8365-topckgen", "syscon";
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| D | mediatek,mt8186-sys-clock.yaml | 21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
31 - mediatek,mt8186-topckgen
53 topckgen: syscon@10000000 {
54 compatible = "mediatek,mt8186-topckgen", "syscon";
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| D | mediatek,mt8195-sys-clock.yaml | 21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
28 - mediatek,mt8195-topckgen
51 topckgen: syscon@10000000 {
52 compatible = "mediatek,mt8195-topckgen", "syscon";
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| D | mediatek,mt8188-sys-clock.yaml | 21 The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
33 - mediatek,mt8188-topckgen
55 compatible = "mediatek,mt8188-topckgen", "syscon";
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| D | mediatek,mt8192-sys-clock.yaml | 20 - mediatek,mt8192-topckgen
43 topckgen: syscon@10000000 {
44 compatible = "mediatek,mt8192-topckgen", "syscon";
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| /Documentation/devicetree/bindings/sound/ |
| D | mt8186-afe-pcm.yaml | 36 mediatek,topckgen:
38 description: The phandle of the mediatek topckgen controller
103 - mediatek,topckgen
122 mediatek,topckgen = <&topckgen>;
125 <&topckgen 15>, //CLK_TOP_AUDIO
126 <&topckgen 16>, //CLK_TOP_AUD_INTBUS
127 <&topckgen 70>, //CLK_TOP_MAINPLL_D2_D4
128 <&topckgen 17>, //CLK_TOP_AUD_1
130 <&topckgen 18>, //CLK_TOP_AUD_2
132 <&topckgen 19>, //CLK_TOP_AUD_ENGEN1
[all …]
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| D | mtk-afe-pcm.txt | 26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
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| D | mt8195-afe-pcm.yaml | 34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
138 - mediatek,topckgen
157 mediatek,topckgen = <&topckgen>;
161 <&topckgen 163>, //CLK_TOP_APLL1
162 <&topckgen 166>, //CLK_TOP_APLL2
163 <&topckgen 233>, //CLK_TOP_APLL12_DIV0
164 <&topckgen 234>, //CLK_TOP_APLL12_DIV1
165 <&topckgen 235>, //CLK_TOP_APLL12_DIV2
166 <&topckgen 236>, //CLK_TOP_APLL12_DIV3
[all …]
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| D | mediatek,mt8188-afe.yaml | 34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
166 - mediatek,topckgen
186 mediatek,topckgen = <&topckgen>;
196 <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0
197 <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1
198 <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
199 <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3
200 <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9
201 <&topckgen 83>, //CLK_TOP_A1SYS_HP
[all …]
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| D | mediatek,mt8365-afe.yaml | 97 <&topckgen CLK_TOP_AUDIO_SEL>,
98 <&topckgen CLK_TOP_AUD_I2S0_M>,
99 <&topckgen CLK_TOP_AUD_I2S1_M>,
100 <&topckgen CLK_TOP_AUD_I2S2_M>,
101 <&topckgen CLK_TOP_AUD_I2S3_M>,
102 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
103 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
104 <&topckgen CLK_TOP_AUD_1_SEL>,
105 <&topckgen CLK_TOP_AUD_2_SEL>,
106 <&topckgen CLK_TOP_APLL_I2S0_SEL>,
[all …]
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| D | mt6797-afe-pcm.txt | 29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
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| D | mt8192-afe-pcm.yaml | 34 mediatek,topckgen:
36 description: The phandle of the mediatek topckgen controller
64 - mediatek,topckgen
86 mediatek,topckgen = <&topckgen>;
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| D | mt8183-afe-pcm.txt | 32 <&topckgen CLK_TOP_MUX_AUDIO>,
33 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
34 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
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| D | mediatek,mt7986-afe.yaml | 152 assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
153 <&topckgen CLK_TOP_AUD_L_SEL>,
154 <&topckgen CLK_TOP_A_TUNER_SEL>;
155 assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
157 <&topckgen CLK_TOP_APLL2_D4>;
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| /Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,audsys.yaml | 75 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
76 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
77 <&topckgen CLK_TOP_AUD_48K_TIMING>,
78 <&topckgen CLK_TOP_AUD_44K_TIMING>,
79 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
80 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
81 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
82 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
83 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
84 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
[all …]
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| /Documentation/devicetree/bindings/media/ |
| D | mediatek,vcodec-decoder.yaml | 175 <&topckgen CLK_TOP_UNIVPLL_D2>,
176 <&topckgen CLK_TOP_CCI400_SEL>,
177 <&topckgen CLK_TOP_VDEC_SEL>,
178 <&topckgen CLK_TOP_VCODECPLL>,
180 <&topckgen CLK_TOP_VENC_LT_SEL>,
181 <&topckgen CLK_TOP_VCODECPLL_370P5>;
190 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
191 <&topckgen CLK_TOP_CCI400_SEL>,
192 <&topckgen CLK_TOP_VDEC_SEL>,
195 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
[all …]
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| D | mediatek,vcodec-encoder.yaml | 162 clocks = <&topckgen CLK_TOP_VENC_SEL>;
164 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
165 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
182 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
184 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
185 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
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| D | mediatek,vcodec-subdev-decoder.yaml | 231 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
235 <&topckgen CLK_TOP_MAINPLL_D4>;
237 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
238 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
257 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
261 <&topckgen CLK_TOP_MAINPLL_D4>;
263 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
264 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
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| /Documentation/devicetree/bindings/net/ |
| D | mediatek-dwmac.yaml | 168 <&topckgen CLK_TOP_ETHER_125M_SEL>,
169 <&topckgen CLK_TOP_ETHER_50M_SEL>,
170 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
171 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
172 <&topckgen CLK_TOP_ETHER_50M_SEL>,
173 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
174 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
175 <&topckgen CLK_TOP_APLL1_D3>,
176 <&topckgen CLK_TOP_ETHERPLL_50M>;
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| D | mediatek,star-emac.yaml | 92 clocks = <&topckgen CLK_TOP_RG_ETH>,
93 <&topckgen CLK_TOP_66M_ETH>,
94 <&topckgen CLK_TOP_133M_ETH>;
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| /Documentation/devicetree/bindings/dsp/ |
| D | mediatek,mt8195-dsp.yaml | 88 clocks = <&topckgen 10>, //CLK_TOP_ADSP
90 <&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS
91 <&topckgen 136>, //CLK_TOP_MAINPLL_D7_D2
93 <&topckgen 34>; //CLK_TOP_AUDIO_H
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| /Documentation/devicetree/bindings/spmi/ |
| D | mtk,spmi-mtk-pmif.yaml | 74 <&topckgen CLK_TOP_SPMI_MST_SEL>;
78 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
79 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
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| /Documentation/devicetree/bindings/power/ |
| D | mediatek,power-controller.yaml | 158 clocks = <&topckgen CLK_TOP_MM_SEL>;
164 clocks = <&topckgen CLK_TOP_MM_SEL>,
165 <&topckgen CLK_TOP_VENC_SEL>;
171 clocks = <&topckgen CLK_TOP_MM_SEL>;
177 clocks = <&topckgen CLK_TOP_MM_SEL>;
184 clocks = <&topckgen CLK_TOP_MM_SEL>,
185 <&topckgen CLK_TOP_VENC_LT_SEL>;
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| /Documentation/devicetree/bindings/spi/ |
| D | mediatek,spi-slave-mt27xx.yaml | 56 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
57 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
|