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/Documentation/devicetree/bindings/powerpc/fsl/
Dsrio-rmu.txt1 Message unit node:
3 For SRIO controllers that implement the message unit as part of the controller
5 node is composed of three types of sub-nodes ("fsl-srio-msg-unit",
6 "fsl-srio-dbell-unit" and "fsl-srio-port-write-unit").
10 - compatible
13 Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu".
18 - reg
20 Value type: <prop-encoded-array>
21 Definition: A standard property. Specifies the physical address and
25 - fsl,liodn
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Dscfg.txt1 Freescale Supplement configuration unit (SCFG)
3 SCFG is the supplemental configuration unit, that provides SoC specific
9 - compatible: should be "fsl,<chip>-scfg"
10 - reg: should contain base address and length of SCFG memory-mapped
15 scfg: global-utilities@fc000 {
16 compatible = "fsl,t1040-scfg";
/Documentation/devicetree/bindings/bus/
Dst,stm32mp25-rifsc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gatien Chevallier <gatien.chevallier@foss.st.com>
19 - RISC registers associated with RISUP logic (resource isolation device unit
20 for peripherals), assign all non-RIF aware peripherals to zero, one or
22 - RIMC registers: associated with RIMU logic (resource isolation master
23 unit), assign all non RIF-aware bus master to one security domain by
28 - RISC registers associated with RISAL logic (resource isolation device unit
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/Documentation/devicetree/bindings/pinctrl/
Dmediatek,mt8188-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui Liu <hui.liu@mediatek.com>
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
25 are defined in <dt-bindings/gpio/gpio.h>.
28 gpio-ranges:
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Dmediatek,mt8186-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
31 gpio-line-names: true
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Dmediatek,mt8195-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
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/Documentation/devicetree/bindings/clock/
Dactions,owl-cmu.txt1 * Actions Semi Owl Clock Management Unit (CMU)
3 The Actions Semi Owl Clock Management Unit generates and supplies clock
9 - compatible: should be one of the following,
10 "actions,s900-cmu"
11 "actions,s700-cmu"
12 "actions,s500-cmu"
13 - reg: physical base address of the controller and length of memory mapped
15 - clocks: Reference to the parent clocks ("hosc", "losc")
16 - #clock-cells: should be 1.
17 - #reset-cells: should be 1.
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/Documentation/devicetree/bindings/
Ddts-coding-style.rst1 .. SPDX-License-Identifier: GPL-2.0
16 ---------------------------
24 * Lowercase characters: [a-z]
25 * Digits: [0-9]
26 * Dash: -
30 * Lowercase characters: [a-z]
31 * Digits: [0-9]
34 3. Unless a bus defines differently, unit addresses shall use lowercase
37 4. Hex values in properties, e.g. "reg", shall use lowercase hex. The address
42 gpi_dma2: dma-controller@a00000 {
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/Documentation/ABI/testing/
Dsysfs-class-iommu-intel-iommu1 What: /sys/class/iommu/<iommu>/intel-iommu/address
6 Physical address of the VT-d DRHD for this IOMMU.
8 intel-iommu with a DMAR DRHD table entry.
10 What: /sys/class/iommu/<iommu>/intel-iommu/cap
16 of this DRHD unit. Format: %llx.
18 What: /sys/class/iommu/<iommu>/intel-iommu/ecap
24 value of this DRHD unit. Format: %llx.
26 What: /sys/class/iommu/<iommu>/intel-iommu/version
32 VT-d VER_REG. Format: %d:%d, major:minor
Dsysfs-devices-mmc8 is enabled, this attribute will indicate the start address of
9 enhanced data area. If not, this attribute will be -EINVAL.
10 Unit Byte. Format decimal.
20 data area. If not, this attribute will be -EINVAL.
21 Unit KByte. Format decimal.
Dsysfs-bus-coresight-devices-etm4x28 Description: (Read) Indicates the number of address comparator pairs that are
76 Description: (Read) Indicates the number of single-shot comparator controls that
83 Description: (Write) Cancels all configuration on a trace unit and set it back
155 Description: (RW) In non-secure state, each bit controls whether instruction
162 Description: (RW) Select which address comparator or pair (of comparators) to
169 Description: (RW) Controls what type of comparison the trace unit performs.
175 Description: (RW) Used to setup single address comparator values.
181 Description: (RW) Used to setup address range comparator values.
212 Description: (RW) Select which counter unit to work with.
238 Description: (RW) Select which resource selection unit to work with.
[all …]
/Documentation/devicetree/bindings/soc/fsl/
Dfsl,layerscape-dcfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/fsl,layerscape-dcfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape Device Configuration Unit
10 - Shawn Guo <shawnguo@kernel.org>
13 DCFG is the device configuration unit, that provides general purpose
15 core start address and release the secondary core from holdoff and
21 - items:
22 - enum:
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Dfsl,layerscape-scfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/fsl,layerscape-scfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Layerscape Supplemental Configuration Unit
10 - Shawn Guo <shawnguo@kernel.org>
13 SCFG is the supplemental configuration unit, that provides SoC specific
20 - enum:
21 - fsl,ls1012a-scfg
22 - fsl,ls1021a-scfg
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/Documentation/gpu/amdgpu/
Damdgpu-glossary.rst7 'Documentation/gpu/amdgpu/display/dc-glossary.rst'.
22 Compute Unit
34 Graphics Address Remapping Table. This is the name we use for the GPUVM
36 (memory or MMIO space) into the GPU's address space so the GPU can access
50 virtual address spaces that can be in flight at any given time. These
51 allow the GPU to remap VRAM and system resources into GPU virtual address
90 Multi-Media HUB
96 PowerPlay Library - PowerPlay is the power management component.
114 System Management Unit
/Documentation/devicetree/bindings/display/
Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
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Dallwinner,sun9i-a80-deu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun9i-a80-deu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 Detail Enhancement Unit
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
19 const: allwinner,sun9i-a80-deu
29 - description: The DEU interface clock
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/Documentation/devicetree/bindings/net/
Dmarvell,orion-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/marvell,orion-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
14 Armada 370, Armada XP, Armada 7k and Armada 8k have an identical unit that
16 8k has a second unit which provides an interface with the xMDIO bus. This
22 - marvell,orion-mdio
23 - marvell,xmdio
36 - compatible
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Dfsl,fman.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
29 Specifies the index of the FMan unit.
31 The cell-index value may be used by the SoC, to identify the
32 FMan unit in the SoC memory map. In the table below,
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/Documentation/devicetree/bindings/mfd/
Daspeed,ast2x00-scu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aspeed System Control Unit
10 The Aspeed System Control Unit manages the global behaviour of the SoC,
14 - Joel Stanley <joel@jms.id.au>
15 - Andrew Jeffery <andrew@aj.id.au>
20 - enum:
21 - aspeed,ast2400-scu
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/Documentation/devicetree/bindings/arm/
Darm,coresight-catu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Coresight Address Translation Unit (CATU)
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
23 The CoreSight Address Translation Unit (CATU) translates addresses between an
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/Documentation/devicetree/bindings/sound/
Dhisilicon,hi6210-i2s.txt5 - compatible: should be one of the following:
6 - "hisilicon,hi6210-i2s"
7 - reg: physical base address of the i2s controller unit and length of
9 - interrupts: should contain the i2s interrupt.
10 - clocks: a list of phandle + clock-specifier pairs, one for each entry
11 in clock-names.
12 - clock-names: should contain following:
13 - "dacodec"
14 - "i2s-base"
15 - dmas: DMA specifiers for tx dma. See the DMA client binding,
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/Documentation/hwmon/
Dnct6775.rst15 Addresses scanned: ISA address retrieved from Super I/O registers
19 * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I
23 Addresses scanned: ISA address retrieved from Super I/O registers
31 Addresses scanned: ISA address retrieved from Super I/O registers
39 Addresses scanned: ISA address retrieved from Super I/O registers
47 Addresses scanned: ISA address retrieved from Super I/O registers
55 Addresses scanned: ISA address retrieved from Super I/O registers
63 Addresses scanned: ISA address retrieved from Super I/O registers
71 Addresses scanned: ISA address retrieved from Super I/O registers
79 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
/Documentation/devicetree/bindings/display/msm/
Dqcom,sc8280xp-dpu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC8280XP Display Processing Unit
10 - Bjorn Andersson <andersson@kernel.org>
13 Device tree bindings for SC8280XP Display Processing Unit.
15 $ref: /schemas/display/msm/dpu-common.yaml#
19 const: qcom,sc8280xp-dpu
23 - description: Address offset and size for mdp register set
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/Documentation/devicetree/bindings/iommu/
Dnvidia,tegra30-smmu.txt1 NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)
4 - compatible : "nvidia,tegra30-smmu"
5 - reg : Should contain 3 register banks(address and length) for each
7 - interrupts : Should contain MC General interrupt.
8 - nvidia,#asids : # of ASIDs
9 - dma-window : IOVA start address and length.
10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
14 compatible = "nvidia,tegra30-smmu";
19 dma-window = <0 0x40000000>; /* IOVA start & length */
/Documentation/devicetree/bindings/interrupt-controller/
Dfsl,mu-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
10 - Frank Li <Frank.Li@nxp.com>
13 The Messaging Unit module enables two processors within the SoC to
23 registers (Processor A-side, Processor B-side).
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
33 - fsl,imx6sx-mu-msi
[all …]

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