Searched +full:up +full:- +full:counter (Results 1 – 25 of 157) sorted by relevance
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| /Documentation/devicetree/bindings/mfd/ |
| D | st,stm32-timers.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
16 - basic timers consist of a 16-bit auto-reload counter driven by a
20 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
24 const: st,stm32-timers
32 clock-names:
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| /Documentation/arch/arm64/ |
| D | amu.rst | 9 Date: 2019-09-10
16 ---------------------
23 system register interface to the counter registers and also supports an
24 optional external memory-mapped interface.
26 Version 1 of the Activity Monitors architecture implements a counter group
27 of four fixed and architecturally defined 64-bit event counters.
29 - CPU cycle counter: increments at the frequency of the CPU.
30 - Constant counter: increments at the fixed frequency of the system
32 - Instructions retired: increments with every architecturally executed
34 - Memory stall cycles: counts instruction dispatch stall cycles caused by
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-counter | 1 What: /sys/bus/counter/devices/counterX/cascade_counts_enable
3 Contact: linux-iio@vger.kernel.org
5 Indicates the cascading of Counts on Counter X.
9 What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select
11 Contact: linux-iio@vger.kernel.org
14 Counter X.
16 MTCLKA-MTCLKB:
20 MTCLKC-MTCLKD:
24 What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select_available
26 Contact: linux-iio@vger.kernel.org
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| D | sysfs-bus-iio-timer-stm32 | 8 - "reset"
11 - "enable"
12 The Counter Enable signal CNT_EN is used
14 - "update"
18 - "compare_pulse"
21 - "OC1REF"
23 - "OC2REF"
25 - "OC3REF"
27 - "OC4REF"
32 - "OC5REF"
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| /Documentation/devicetree/bindings/timer/ |
| D | ti,keystone-timer.txt | 3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 It is global timer is a free running up-counter and can generate interrupt
10 when the counter reaches preset counter values.
17 - compatible : should be "ti,keystone-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupt generated by the timer.
20 - clocks : the clock feeding the timer clock.
25 compatible = "ti,keystone-timer";
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| D | ti,da830-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,da830-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kousik Sanagavarapu <five231003@gmail.com>
13 This is a 64-bit timer found on TI's DaVinci architecture devices. The timer
14 can be configured as a general-purpose 64-bit timer, dual general-purpose
15 32-bit timers. When configured as dual 32-bit timers, each half can operate
18 The timer is a free running up-counter and can generate interrupts when the
19 counter reaches preset counter values.
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| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
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| D | nvidia,tegra-timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
21 # Either a single combined interrupt or up to 14 individual interrupts
27 - if:
31 - items:
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| D | arm,arch_timer_mmio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
14 ARM cores may have a memory mapped architected timer, which provides up to 8
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
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| D | samsung,exynos4210-mct.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
23 - enum:
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| /Documentation/devicetree/bindings/power/reset/ |
| D | atmel,at91sam9260-shdwc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/atmel,at91sam9260-shdwc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
14 and VDDCORE and the wake-up detection on debounced input lines.
19 - atmel,at91sam9260-shdwc
20 - atmel,at91sam9rl-shdwc
21 - atmel,at91sam9x5-shdwc
29 atmel,wakeup-mode:
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| /Documentation/power/ |
| D | runtime_pm.rst | 5 (C) 2009-2011 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
18 put their PM-related work items. It is strongly recommended that pm_wq be
20 them to be synchronized with system-wide power transitions (suspend to RAM,
53 The ->runtime_suspend(), ->runtime_resume() and ->runtime_idle() callbacks
57 1. PM domain of the device, if the device's PM domain object, dev->pm_domain,
60 2. Device type of the device, if both dev->type and dev->type->pm are present.
62 3. Device class of the device, if both dev->class and dev->class->pm are
65 4. Bus type of the device, if both dev->bus and dev->bus->pm are present.
69 dev->driver->pm directly (if present).
73 and bus type. Moreover, the high-priority one will always take precedence over
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| /Documentation/admin-guide/acpi/ |
| D | cppc_sysfs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
15 to request performance levels and to measure per-cpu delivered performance.
27 $ ls -lR /sys/devices/system/cpu/cpu0/acpi_cppc/
30 -r--r--r-- 1 root root 65536 Mar 5 19:38 feedback_ctrs
31 -r--r--r-- 1 root root 65536 Mar 5 19:38 highest_perf
32 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_freq
33 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_nonlinear_perf
34 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_perf
35 -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_freq
36 -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_perf
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| /Documentation/trace/ |
| D | fprobe.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Fprobe - Function entry/exit probe
22 The fprobe is a wrapper of ftrace (+ kretprobe-like return callback) to
23 attach callbacks to multiple function entry and exit. User needs to set up
29 .. code-block:: c
40 The register_fprobe() enables a fprobe by function-name filters.
45 The register_fprobe_ips() enables a fprobe by ftrace-location addresses.
48 .. code-block:: c
57 .. code-block:: c
92 .. code-block:: c
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| /Documentation/timers/ |
| D | timekeeping.rst | 10 If you grep through the kernel source you will find a number of architecture-
12 architecture-specific overrides of the sched_clock() function and some
17 on this timeline, providing facilities such as high-resolution timers.
23 -------------
30 Typically the clock source is a monotonic, atomic counter which will provide
31 n bits which count from 0 to (2^n)-1 and then wraps around to 0 and start over.
36 shall be as stable and correct as possible as compared to a real-world wall
41 the counter register is read in two phases on the bus lowest 16 bits first
42 and the higher 16 bits in a second bus cycle with the counter bits
44 values from the counter.
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| D | hpet.rst | 8 Each HPET has one fixed-rate counter (at 10+ MHz, hence "High Precision")
9 and up to 32 comparators. Normally three or more comparators are provided,
13 independent of each other ... these share a counter, complicating resets.
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| /Documentation/admin-guide/perf/ |
| D | arm-cmn.rst | 5 CMN-600 is a configurable mesh interconnect consisting of a rectangular
6 grid of crosspoints (XPs), with each crosspoint supporting up to two
11 counts up to 4 event signals from the connected device nodes and/or the
12 XP itself. Overflow from these local counters is accumulated in up to 8
14 overall PMU control and interrupts for global counter overflow.
17 ----------
20 see /sys/bus/event_source/devices/arm_cmn_0. Multi-chip systems may link
21 more than one CMN together via external CCIX links - in this situation,
26 definitions - "type" selects the respective node type, and "eventid" the
30 * Since RN-D nodes do not have any distinct events from RN-I nodes, they
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| /Documentation/core-api/ |
| D | errseq.rst | 13 It's implemented as an unsigned 32-bit value. The low order bits are
15 are used as a counter. This is done with atomics instead of locking so that
19 frequently, since we have so few bits to use as a counter.
21 To mitigate this, the bit between the error value and counter is used as
23 recorded. That allows us to avoid bumping the counter if no one has
26 Thus we end up with a value that looks something like this:
28 +--------------------------------------+----+------------------------+
30 +--------------------------------------+----+------------------------+
31 | counter | SF | errno |
32 +--------------------------------------+----+------------------------+
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| D | local_ops.rst | 51 their UP variant must be kept. It typically means removing LOCK prefix (on
53 not have a different behavior between SMP and UP, including
54 ``asm-generic/local.h`` in your architecture's ``local.h`` is sufficient.
72 different CPU between getting the per-cpu variable and doing the
78 -rt kernels.
110 If you are already in a preemption-safe context, you can use
131 the ``local_t`` variable as a counter of bytes written in a buffer: there should
132 be a ``smp_wmb()`` between the buffer write and the counter increment and also a
133 ``smp_rmb()`` between the counter read and the buffer read.
136 Here is a sample module which implements a basic per cpu counter using
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| /Documentation/arch/mips/ |
| D | ingenic-tcu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Ingenic JZ47xx SoCs Timer/Counter Unit hardware
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
8 hardware block. It features up to eight channels, that can be used as
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
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| /Documentation/networking/ |
| D | nf_flowtable.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 --------
28 n-tuple selectors: layer 2 protocol encapsulation (VLAN and PPPoE), layer 3
51 _________ __________ --------- _____\/_____
53 --> ingress ---> prerouting ---> |decision| | postrouting |--> neigh_xmit
54 \_________/ \__________/ ---------- \____________/ ^
58 __\/___ | | forward |------------ |
59 |-----| | \_________/ |
60 |-----| | 'flow offload' rule |
61 |-----| | adds entry to |
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| /Documentation/bpf/ |
| D | ringbuf.rst | 12 ----------
18 - more efficient memory utilization by sharing ring buffer across CPUs;
19 - preserving ordering of events that happen sequentially in time, even across
23 Both are a result of a choice to have per-CPU perf ring buffer. Both can be
25 problem could technically be solved for perf buffer with some in-kernel
30 ------------------
56 The approach chosen has an advantage of re-using existing BPF map
62 combined with ``ARRAY_OF_MAPS`` and ``HASH_OF_MAPS`` map-in-maps to implement
66 with hashed task's tgid being a look up key to preserve order, but reduce
75 - variable-length records;
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| /Documentation/virt/kvm/x86/ |
| D | timekeeping.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
63 -------------- | +->| GATE TIMER 0 |
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| /Documentation/devicetree/bindings/perf/ |
| D | starfive,jh8100-starlink-pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
14 shared L3 memory system. The PMU support overflow interrupt, up to
16 counter. StarFive's JH8100 StarLink PMU is accessed via MMIO.
20 const: starfive,jh8100-starlink-pmu
29 - compatible
30 - reg
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| /Documentation/arch/powerpc/ |
| D | imc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 IMC (In-Memory Collection Counters)
17 IMC (In-Memory collection counters) is a hardware monitoring facility that
19 on-chip but off-core), Core level and Thread level.
22 (On-Chip Controller) complex. The microcode collects the counter data and moves
23 the nest IMC counter data to memory.
33 - Event name
34 - Event Offset
35 - Event description
39 - Event scale
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