Searched +full:usb +full:- +full:ehci (Results 1 – 25 of 32) sorted by relevance
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| /Documentation/devicetree/bindings/usb/ |
| D | generic-ehci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-ehci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: USB EHCI Controller
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
13 - $ref: usb-hcd.yaml
14 - if:
19 const: ibm,usb-ehci-440epx
28 - items:
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| D | brcm,bcm7445-ehci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/brcm,bcm7445-ehci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB USB EHCI Controller
10 - $ref: usb-hcd.yaml
13 - Al Cooper <alcooperx@gmail.com>
17 const: brcm,bcm7445-ehci
27 description: Clock specifier for the EHCI clock
29 clock-names:
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| D | ehci-st.txt | 1 ST USB EHCI controller
4 - compatible : must be "st,st-ehci-300x"
5 - reg : physical base addresses of the controller and length of memory mapped
7 - interrupts : one EHCI interrupt should be described here
8 - pinctrl-names : a pinctrl state named "default" must be defined
9 - pinctrl-0 : phandle referencing pin configuration of the USB controller
10 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
11 - clocks : phandle list of usb clocks
12 - clock-names : should be "ic" for interconnect clock and "clk48"
13 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
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| D | marvell,pxau2o-ehci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/marvell,pxau2o-ehci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell PXA/MMP EHCI
11 - Lubomir Rintel <lkundrak@v3.sk>
14 - $ref: usb-hcd.yaml#
18 const: marvell,pxau2o-ehci
29 clock-names:
35 phy-names:
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| D | ci-hdrc-usb2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: USB2 ChipIdea USB controller
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
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| D | nvidia,tegra20-ehci.txt | 1 Tegra SOC USB controllers
3 The device node for a USB controller that is part of a Tegra
9 - compatible : For Tegra20, must contain "nvidia,tegra20-ehci".
10 For Tegra30, must contain "nvidia,tegra30-ehci". Otherwise, must contain
11 "nvidia,<chip>-ehci" plus at least one of the above, where <chip> is
13 - nvidia,phy : phandle of the PHY that the controller is connected to.
14 - clocks : Must contain one entry, for the module clock.
15 See ../clocks/clock-bindings.txt for details.
16 - resets : Must contain an entry for each entry in reset-names.
18 - reset-names : Must include the following entries:
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| D | atmel-usb.txt | 1 Atmel SOC USB controllers
6 - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
8 - reg: Address and length of the register set for the device
9 - interrupts: Should contain ohci interrupt
10 - clocks: Should reference the peripheral, host and system clocks
11 - clock-names: Should contain three strings
15 - num-ports: Number of ports.
16 - atmel,vbus-gpio: If present, specifies a gpio that needs to be
18 - atmel,oc-gpio: If present, specifies a gpio that needs to be
22 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
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| D | samsung,exynos-usb2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/samsung,exynos-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC USB 2.0 EHCI/OHCI Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - samsung,exynos4210-ehci
16 - samsung,exynos4210-ohci
21 clock-names:
23 - const: usbhost
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| /Documentation/usb/ |
| D | ehci.rst | 2 EHCI driver
5 27-Dec-2002
7 The EHCI driver is used to talk to high speed USB 2.0 devices using
8 USB 2.0-capable host controller hardware. The USB 2.0 standard is
9 compatible with the USB 1.1 standard. It defines three transfer speeds:
11 - "High Speed" 480 Mbit/sec (60 MByte/sec)
12 - "Full Speed" 12 Mbit/sec (1.5 MByte/sec)
13 - "Low Speed" 1.5 Mbit/sec
15 USB 1.1 only addressed full speed and low speed. High speed devices
16 can be used on USB 1.1 systems, but they slow down to USB 1.1 speeds.
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| D | index.rst | 2 USB support
12 ehci
14 functionfs-desc
21 gadget-testing
23 mass-storage
27 raw-gadget
30 usb-serial
32 usb-help
|
| /Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 1 OMAP HS USB Host
5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
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| /Documentation/arch/x86/ |
| D | earlyprintk.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Mini-HOWTO for using the earlyprintk=dbgp boot option with a
10 You need two computers, the 'USB debug key' special gadget and
11 two USB cables, connected like this::
13 [host/target] <-------> [USB debug key] <-------> [client/console]
18 a) Host/target system needs to have USB debug port capability.
21 the lspci -vvv output::
23 # lspci -vvv
25 …00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 03) (p…
27 …Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisIN…
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-pci-drivers-ehci_hcd | 2 /sys/bus/usb/devices/usbN/../companion
7 PCI-based EHCI USB controllers (i.e., high-speed USB-2.0
9 "companion" full/low-speed USB-1.1 controllers. When a
10 high-speed device is plugged in, the connection is routed
11 to the EHCI controller; when a full- or low-speed device
15 Sometimes you want to force a high-speed device to connect
23 For example: To force the high-speed device attached to
26 echo 4 >/sys/bus/usb/devices/usb2/../companion
28 To return the port to high-speed operation::
30 echo -4 >/sys/bus/usb/devices/usb2/../companion
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 1 * UCTL USB controller glue
4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
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| /Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | wii.txt | 11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
42 - reg : should contain the PI registers location and length
52 - #interrupt-cells : <1>
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| /Documentation/devicetree/bindings/phy/ |
| D | renesas,rcar-gen2-usb-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen2 USB PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,usb-phy-r8a7742 # RZ/G1H
17 - renesas,usb-phy-r8a7743 # RZ/G1M
18 - renesas,usb-phy-r8a7744 # RZ/G1N
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| D | brcm,brcmstb-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,brcmstb-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB USB PHY
9 description: Broadcom's PHY that handles EHCI/OHCI and/or XHCI
12 - Al Cooper <alcooperx@gmail.com>
13 - Rafał Miłecki <rafal@milecki.pl>
18 - brcm,bcm4908-usb-phy
19 - brcm,bcm7211-usb-phy
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| D | renesas,usb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 2.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - items:
16 - enum:
17 - renesas,usb2-phy-r8a77470 # RZ/G1C
18 - renesas,usb2-phy-r9a08g045 # RZ/G3S
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| /Documentation/devicetree/bindings/ |
| D | resource-names.txt | 11 ----------------- ---------------------------
12 reg reg-names
13 clocks clock-names
14 interrupts interrupt-names
18 The -names property must be used in conjunction with the normal resource
23 l4-abe {
24 compatible = "simple-bus";
25 #address-cells = <2>;
26 #size-cells = <1>;
33 reg-names = "mpu", "dat",
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| D | xilinx.txt | 10 Each IP-core has a set of parameters which the FPGA designer can use to
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
33 (generic-name): an open firmware-style name that describes the
36 (ip-core-name): the name of the ip block (given after the BEGIN
38 and all underscores '_' converted to dashes '-'.
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| /Documentation/arch/arm/stm32/ |
| D | stm32mp13-overview.rst | 6 ------------
8 The STM32MP131/STM32MP133/STM32MP135 are Cortex-A MPU aimed at various applications.
11 - One Cortex-A7 application core
12 - Standard memories interface support
13 - Standard connectivity, widely inherited from the STM32 MCU family
14 - Comprehensive security support
18 - Cortex-A7 core running up to @900MHz
19 - FMC controller to connect SDRAM, NOR and NAND memories
20 - QSPI
21 - SD/MMC/SDIO support
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| D | stm32mp151-overview.rst | 6 ------------
8 The STM32MP151 is a Cortex-A MPU aimed at various applications.
11 - Single Cortex-A7 application core
12 - Standard memories interface support
13 - Standard connectivity, widely inherited from the STM32 MCU family
14 - Comprehensive security support
18 - Cortex-A7 core running up to @800MHz
19 - FMC controller to connect SDRAM, NOR and NAND memories
20 - QSPI
21 - SD/MMC/SDIO support
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| /Documentation/devicetree/bindings/pci/ |
| D | renesas,pci-rcar-gen2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marek.vasut+renesas@gmail.com>
11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 This is the bridge used internally to connect the USB controllers to the
15 AHB. There is one bridge instance per USB port connected to the internal
16 OHCI and EHCI controllers.
21 - items:
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| /Documentation/leds/ |
| D | ledtrig-usbport.rst | 2 USB port LED trigger
5 This LED trigger can be used for signalling to the user a presence of USB device
9 It requires selecting USB ports that should be observed. All available ones are
13 Please note that this trigger allows selecting multiple USB ports for a single
18 1) Device with single USB LED and few physical ports
22 USB device.
27 Some devices may have one controller per PHY standard. E.g. USB 3.0 physical
28 port may be handled by ohci-platform, ehci-platform and xhci-hcd. If there is
38 Documentation/ABI/testing/sysfs-class-led-trigger-usbport
40 Example use-case::
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| /Documentation/driver-api/usb/ |
| D | dma.rst | 1 USB DMA
4 In Linux 2.5 kernels (and later), USB device drivers have additional control
6 in the kernel usb programming guide (kerneldoc, from the source code).
11 The big picture is that USB drivers can continue to ignore most DMA issues,
12 though they still must provide DMA-ready buffers (see
13 Documentation/core-api/dma-api-howto.rst). That's how they've worked through
14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
19 manage dma mappings for existing dma-ready buffers (see below).
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