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/Documentation/devicetree/bindings/usb/
Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
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Dam33xx-usb.txt3 - compatible: ti,am33xx-usb
4 - reg: offset and length of the usbss register sets
5 - ti,hwmods : must be "usb_otg_hs"
8 at least a control module node, USB node and a PHY node. The second USB
13 - compatible: ti,am335x-usb-ctrl-module
14 - reg: offset and length of the "USB control registers" in the "Control
15 Module" block. A second offset and length for the USB wake up control
17 - reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
18 the USB wake up control register.
20 USB PHY
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/Documentation/devicetree/bindings/soc/imx/
Dfsl,imx8mp-hsio-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HSIO blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the high-speed IO
15 (USB an PCIe) peripherals located in the HSIO domain of the SoC.
20 - const: fsl,imx8mp-hsio-blk-ctrl
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/Documentation/devicetree/bindings/phy/
Dmarvell,armada-cp110-utmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Konstantin Porotchkin <kostap@marvell.com>
14 On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
15 Each of two exiting UTMI PHYs could be connected to either USB host or USB device
17 The USB device controller can only be connected to a single UTMI PHY port
18 0.H----- USB HOST0
19 UTMI PHY0 --------/
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Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
11 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
19 Two set of 3-tuple setting for each (up to 3)
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/Documentation/leds/
Dleds-class.rst8 of the LED (taking a value 0-max_brightness). Most LEDs don't have hardware
9 brightness support so will just be turned on for non-zero brightness settings.
14 existing subsystems with minimal additional code. Examples are the disk-activity,
15 nand-disk and sharpsl-charge triggers. With led triggers disabled, the code
48 - devicename:
57 - color:
59 include/dt-bindings/leds/common.h.
61 - function:
63 include/dt-bindings/leds/common.h.
66 to linux-leds@vger.kernel.org.
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