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/Documentation/devicetree/bindings/phy/
Drenesas,usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 2.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - items:
16 - enum:
17 - renesas,usb2-phy-r8a77470 # RZ/G1C
18 - renesas,usb2-phy-r9a08g045 # RZ/G3S
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Dphy-hisi-inno-usb2.txt1 Device tree bindings for HiSilicon INNO USB2 PHY
4 - compatible: Should be one of the following strings:
5 "hisilicon,inno-usb2-phy",
6 "hisilicon,hi3798cv200-usb2-phy".
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
13 - #address-cells: Must be 1.
14 - #size-cells: Must be 0.
16 The INNO USB2 PHY device should be a child node of peripheral controller that
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Dsocionext,uniphier-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB2 PHY
10 This describes the devicetree bindings for PHY interface built into
11 USB2 controller implemented on Socionext UniPhier SoCs.
12 Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
13 controller doesn't include its own High-Speed PHY. This needs to specify
14 USB2 PHY instead of USB3 HS-PHY.
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Dsamsung,usb2-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P/Exynos SoC USB 2.0 PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 The first phandle argument in the PHY specifier identifies the PHY, its
18 0 - USB device ("device"),
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Damlogic,meson8b-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
15 - items:
16 - enum:
17 - amlogic,meson8-usb2-phy
18 - amlogic,meson8b-usb2-phy
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Dti,omap-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,omap-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OMAP USB2 PHY
10 - Kishon Vijay Abraham I <kishon@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - items:
17 - enum:
18 - ti,dra7x-usb2
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Dphy-lantiq-rcu-usb2.txt1 Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
4 This binding describes the USB PHY hardware provided by the RCU module on the
9 -------------------------------------------------------------------------------
11 - compatible : Should be one of
12 "lantiq,ase-usb2-phy"
13 "lantiq,danube-usb2-phy"
14 "lantiq,xrx100-usb2-phy"
15 "lantiq,xrx200-usb2-phy"
16 "lantiq,xrx300-usb2-phy"
17 - reg : Defines the following sets of registers in the parent
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Damlogic,g12a-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/amlogic,g12a-usb2-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic G12A USB2 PHY
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,g12a-usb2-phy
17 - amlogic,a1-usb2-phy
25 clock-names:
27 - const: xtal
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Damlogic,meson-gxl-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/amlogic,meson-gxl-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic Meson GXL USB2 PHY
10 - Neil Armstrong <neil.armstrong@linaro.org>
14 const: amlogic,meson-gxl-usb2-phy
22 clock-names:
24 - const: phy
29 reset-names:
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Dst,stih407-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/st,stih407-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STiH407 USB PHY controller
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 The USB picoPHY device is the PHY for both USB2 and USB3 host controllers
14 (when controlling usb2/1.1 devices) available on STiH407 SoC family from
19 const: st,stih407-usb2-phy
23 $ref: /schemas/types.yaml#/definitions/phandle-array
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Dnuvoton,ma35d1-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nuvoton,ma35d1-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton MA35D1 USB2 phy
10 - Hui-Ping Chen <hpchen0nvt@gmail.com>
15 - nuvoton,ma35d1-usb2-phy
17 "#phy-cells":
26 phandle to syscon for checking the PHY clock status.
29 - compatible
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Dbrcm,kona-usb2-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,kona-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family USB 2.0 PHY
10 - Florian Fainelli <f.fainelli@gmail.com>
14 const: brcm,kona-usb2-phy
19 '#phy-cells':
23 - compatible
24 - reg
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Dbrcm,ns2-drd-phy.txt1 BROADCOM NORTHSTAR2 USB2 (DUAL ROLE DEVICE) PHY
4 - compatible: brcm,ns2-drd-phy
5 - reg: offset and length of the NS2 PHY related registers.
6 - reg-names
8 icfg - for DRD ICFG configurations
9 rst-ctrl - for DRD IDM reset
10 crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
11 usb2-strap - for port over current polarity reversal
12 - #phy-cells: Must be 0. No args required.
13 - vbus-gpios: vbus gpio binding
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Dti-phy.txt1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
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Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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Dmarvell,armada-3700-utmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell Armada UTMI/UTMI+ PHY
11 - Miquel Raynal <miquel.raynal@bootlin.com>
15 the USB2 and USB3 specifications and supports OTG. The other one is USB2
17 a slightly different UTMI PHY.
22 - marvell,a3700-utmi-host-phy
23 - marvell,a3700-utmi-otg-phy
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Dbcm-ns-usb2-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/bcm-ns-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Northstar USB 2.0 PHY
10 To initialize USB 2.0 PHY driver needs to setup PLL correctly.
11 To do this it requires passing phandle to the USB PHY reference clock.
14 - Rafał Miłecki <rafal@milecki.pl>
18 const: brcm,ns-usb2-phy
22 - maxItems: 1
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Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dsunplus,sp7021-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/sunplus,sp7021-usb2-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus SP7021 USB 2.0 PHY Controller
11 - Vincent Shih <vincent.sunplus@gmail.com>
15 const: sunplus,sp7021-usb2-phy
19 - description: UPHY register region
20 - description: MOON4 register region
22 reg-names:
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Dkeystone-usb-phy.txt1 TI Keystone USB PHY
4 - compatible: should be "ti,keystone-usbphy".
5 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
7 - reg : Address and length of the usb phy control register set.
9 The main purpose of this PHY driver is to enable the USB PHY reference clock
10 gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
11 an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
12 phy node in the USB Glue layer driver node.
15 compatible = "ti,keystone-usbphy";
16 #address-cells = <1>;
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/Documentation/devicetree/bindings/usb/
Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
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Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: USB2 ChipIdea USB controller
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
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/Documentation/driver-api/phy/
Dsamsung-usb2.rst2 Samsung USB 2.0 PHY adaptation layer
6 --------------
8 The architecture of the USB 2.0 PHY module in Samsung SoCs is similar
10 create a one driver that would fit all these PHY controllers. Often
12 registers of the PHY. In some rare cases the order of register writes or
13 the PHY powering up process had to be altered. This adaptation layer is
18 --------------------
20 - phy-samsung-usb2.c
22 the probe function and provides two callbacks to the Generic PHY
24 phy. They carry out the common work that has to be done on all version
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