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/Documentation/devicetree/bindings/phy/
Dqcom,sc8280xp-qmp-usb3-uni-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (USB, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,ipq6018-qmp-usb3-phy
20 - qcom,ipq8074-qmp-usb3-phy
21 - qcom,ipq9574-qmp-usb3-phy
[all …]
Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
[all …]
Dqcom,sc8280xp-qmp-usb43dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,sc7180-qmp-usb3-dp-phy
20 - qcom,sc7280-qmp-usb3-dp-phy
21 - qcom,sc8180x-qmp-usb3-dp-phy
[all …]
Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
10 This describes the devicetree bindings for PHY interfaces built into
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
Dbcm-ns-usb3-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/bcm-ns-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Northstar USB 3.0 PHY
10 Initialization of USB 3.0 PHY depends on Northstar version. There are currently
18 - Rafał Miłecki <rafal@milecki.pl>
23 - brcm,ns-ax-usb3-phy
24 - brcm,ns-bx-usb3-phy
30 usb3-dmp-syscon:
[all …]
Dqcom,msm8998-qmp-usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (USB, MSM8998)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for USB-C on
19 - qcom,msm8998-qmp-usb3-phy
20 - qcom,qcm2290-qmp-usb3-phy
21 - qcom,sdm660-qmp-usb3-phy
[all …]
Damlogic,g12a-usb3-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
[all …]
Dallwinner,sun50i-h6-usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Allwinner H6 USB3 PHY
11 - Ondrej Jirman <megous@megous.com>
16 - allwinner,sun50i-h6-usb3-phy
27 "#phy-cells":
31 - compatible
32 - reg
[all …]
Dphy-rockchip-typec.txt1 * ROCKCHIP type-c PHY
2 ---------------------
5 - compatible : must be "rockchip,rk3399-typec-phy"
6 - reg: Address and length of the usb phy control register set
7 - rockchip,grf : phandle to the syscon managing the "general
9 - clocks : phandle + clock specifier for the phy clocks
10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
14 - resets : a list of phandle + reset specifier pairs
[all …]
Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dsocionext,uniphier-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB2 PHY
10 This describes the devicetree bindings for PHY interface built into
12 Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
13 controller doesn't include its own High-Speed PHY. This needs to specify
14 USB2 PHY instead of USB3 HS-PHY.
17 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
[all …]
Dkeystone-usb-phy.txt1 TI Keystone USB PHY
4 - compatible: should be "ti,keystone-usbphy".
5 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
7 - reg : Address and length of the usb phy control register set.
9 The main purpose of this PHY driver is to enable the USB PHY reference clock
10 gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
11 an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
12 phy node in the USB Glue layer driver node.
15 compatible = "ti,keystone-usbphy";
16 #address-cells = <1>;
[all …]
Dti-phy.txt1 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11 e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
14 e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
[all …]
Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dphy-mvebu.txt1 * Marvell MVEBU SATA PHY
3 Power control for the SATA phy found on Marvell MVEBU SoCs.
5 This document extends the binding described in phy-bindings.txt
9 - reg : Offset and length of the register set for the SATA device
10 - compatible : Should be "marvell,mvebu-sata-phy"
11 - clocks : phandle of clock and specifier that supplies the device
12 - clock-names : Should be "sata"
15 sata-phy@84000 {
16 compatible = "marvell,mvebu-sata-phy";
19 clock-names = "sata";
[all …]
Dhisilicon,hi3660-usb3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,hi3660-usb3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon Kirin 960 USB PHY
10 - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
12 Bindings for USB3 PHY on HiSilicon Kirin 960.
16 const: hisilicon,hi3660-usb-phy
18 "#phy-cells":
21 hisilicon,pericrg-syscon:
[all …]
/Documentation/devicetree/bindings/soc/socionext/
Dsocionext,uniphier-dwc3-glue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
10 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
15 USB3.0 component.
20 - enum:
21 - socionext,uniphier-pro4-dwc3-glue
[all …]
/Documentation/devicetree/bindings/soc/hisilicon/
Dhisilicon,hi3660-usb3-otg-bc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/hisilicon/hisilicon,hi3660-usb3-otg-bc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
15 - const: hisilicon,hi3660-usb3-otg-bc
16 - const: syscon
17 - const: simple-mfd
22 usb-phy:
23 $ref: /schemas/phy/hisilicon,hi3660-usb3.yaml
[all …]
/Documentation/devicetree/bindings/usb/
Damlogic,meson-g12a-usb-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/amlogic,meson-g12a-usb-ctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
15 in host-only mode, and a DWC2 IP Core configured for USB2 peripheral mode
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
20 One of the USB2 PHYs can be re-routed in peripheral mode to a DWC2 USB IP.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
[all …]
Dti,keystone-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Roger Quadros <rogerq@kernel.org>
15 - enum:
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
22 '#address-cells':
25 '#size-cells':
[all …]
Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek USB3 xHCI
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
[all …]
Drockchip,rk3399-dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-dwc3
16 '#address-cells':
19 '#size-cells':
26 - description:
28 - description:
[all …]

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