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/Documentation/devicetree/bindings/interrupt-controller/
Dopencores,or1k-pic.txt5 - compatible : should be "opencores,or1k-pic-level" for variants with
6 level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
Dcdns,xtensa-pic.txt12 core variants it may be mapped to different internal IRQ.
Dst,spear3xx-shirq.txt7 There can be multiple groups available on SPEAr3xx variants but not
/Documentation/scheduler/
Dcompletion.rst39 - the waiting part through a call to one of the variants of wait_for_completion(),
79 variants of wait_for_completion(), as it must be assured that memory de-allocation
125 To emphasise this again: in particular when using some of the waiting API variants
127 _killable() and _interruptible()) variants, the wait might complete
174 uninterruptible. wait_for_completion() and its variants are only safe
180 As all variants of wait_for_completion() can (obviously) block for a long
185 wait_for_completion*() variants available:
188 The below variants all return status and this status should be checked in
228 Further variants include _killable which uses TASK_KILLABLE as the
235 The _io variants wait_for_completion_io() behave the same as the non-_io
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/Documentation/devicetree/bindings/arm/
Darm,versatile.yaml13 The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards
19 variants.
/Documentation/fb/
Ds3fb.rst10 S3 Trio64 (and variants V+, UV+, V2/DX, V2/GX)
11 S3 Virge (and variants VX, DX, GX and GX2+)
26 * 4 bpp pseudocolor modes (with 18bit palette, two variants)
/Documentation/driver-api/
Dvfio-pci-device-specific-driver-acceptance.rst3 Acceptance criteria for vfio-pci device specific driver variants
19 variants may interact with parent devices (ex. SR-IOV PF in support of
/Documentation/core-api/
Dtimekeeping.rst12 The recommended simplest form returns an opaque ktime_t, with variants
62 For all of the above, there are variants that return the time in a
100 Some additional variants exist for more specialized cases:
138 These variants are safe to call from any context, including from
Dasm-annotations.rst112 architecture specific ``__ALIGN`` bytes. There are also ``_NOALIGN`` variants
149 one. ``_NOALIGN`` variants exist too. The use is the same as for the ``FUNC``
194 * ``SYM_DATA`` and ``SYM_DATA_LOCAL`` are variants for simple, mostly one-line
211 symbol marked by them. They are used either in ``_LABEL`` variants of the
Dboot-time-mm.rst18 particular node in a NUMA system. There are API variants that panic
/Documentation/hwmon/
Dintel-m10-bmc-hwmon.rst28 reprogramed to some variants in order to support different Intel
30 variants, but now it only supports the BMC for Intel PAC N3000.
Demc2103.rst33 The 2103-2 and 2103-4 variants have a third temperature sensor, which can
/Documentation/arch/x86/
Dmds.rst10 on internal buffers in Intel CPUs. The variants are:
73 All variants have the same mitigation strategy at least for the single CPU
182 and not by any other MDS variant. The other MDS variants cannot be
184 the Load Ports are shared. So on CPUs affected by other variants, the
203 The mitigation is hooked into all variants of halt()/mwait(), but does
/Documentation/devicetree/bindings/pci/
Dintel,ixp4xx-pci.yaml23 description: The two supported variants are ixp42x and ixp43x,
24 though more variants may exist.
/Documentation/RCU/
Drcu.rst41 Preemptible variants of RCU (CONFIG_PREEMPT_RCU) get the
46 critical sections. These variants of RCU detect grace periods
/Documentation/admin-guide/hw-vuln/
Dmds.rst26 Not all processors are affected by all variants of MDS, but the mitigation
153 other variants cannot be protected against cross Hyper-Thread attacks.
211 cross Hyper-Threads when entering idle states. Some XEON PHI variants allow
216 XEON PHI is not affected by the other MDS variants and MSBDS is mitigated
225 All MDS variants except MSBDS can be attacked cross Hyper-Threads. That
/Documentation/devicetree/bindings/rtc/
Depson,rtc7301.yaml10 The only difference between the two variants is the packaging.
/Documentation/bpf/
Dmap_hash.rst6 BPF_MAP_TYPE_HASH, with PERCPU and LRU Variants
28 variants add LRU semantics to their respective hash tables. An LRU hash
227 ``BPF_MAP_TYPE_LRU_HASH`` and variants
254 variants. See the dot file source for kernel function name code references.
/Documentation/i2c/
Dslave-eeprom-backend.rst13 variants are also supported. The name needed for instantiating has the form
/Documentation/power/regulator/
Ddesign.rst14 of the system - software-equivalent variants of the same chip may
/Documentation/devicetree/bindings/mtd/partitions/
Dbrcm,trx.txt21 There are two existing/known TRX variants:
/Documentation/devicetree/bindings/mfd/
Dbrcm,twd.yaml14 BCM63xx, BCM7038). There are few variants available (they differ slightly in
/Documentation/devicetree/bindings/clock/
Dqcom,gcc-msm8974.yaml16 domains on MSM8974 (all variants) and MSM8226.
/Documentation/devicetree/bindings/dma/
Dowl-dma.yaml12 independent DMA channels for the S500 and S900 SoC variants.
/Documentation/devicetree/bindings/iio/temperature/
Dmaxim,max31855k.yaml20 the thermocouple type specific variants.

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