Searched full:vclk (Results 1 – 9 of 9) sorted by relevance
| /Documentation/devicetree/bindings/media/ |
| D | aspeed-video.txt | 13 - clock-names: "vclk" and "eclk"
29 clock-names = "vclk", "eclk";
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| D | renesas,fcp.yaml | 80 - const: vclk
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| D | renesas,vsp1.yaml | 89 - const: vclk
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| /Documentation/devicetree/bindings/display/samsung/ |
| D | samsung,fimd.yaml | 46 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
119 samsung,invert-vclk:
185 samsung,invert-vclk;
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| /Documentation/devicetree/bindings/display/ |
| D | renesas,rzg2l-du.yaml | 44 - const: vclk
130 clock-names = "aclk", "pclk", "vclk";
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| D | xylon,logicvc-display.yaml | 45 # vclk is required and must be provided as first item.
46 - const: vclk
228 clock-names = "vclk", "lvdsclk";
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| D | amlogic,meson-vpu.yaml | 20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
53 The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | renesas,dsi.yaml | 66 - const: vclk
156 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
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| /Documentation/gpu/ |
| D | meson.rst | 19 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
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