Searched full:vdosys1 (Results 1 – 3 of 3) sorted by relevance
| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,ethdr.yaml | 156 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
157 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
158 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
159 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
160 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
161 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
162 <&vdosys1 CLK_VDO1_26M_SLOW>,
163 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
164 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
165 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
[all …]
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| D | mediatek,padding.yaml | 15 specified colors. Due to hardware design, Mixer in VDOSYS1 requires
79 clocks = <&vdosys1 CLK_VDO1_PADDING0>;
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| /Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,mmsys.yaml | 35 - mediatek,mt8188-vdosys1
39 - mediatek,mt8195-vdosys1
45 - description: vdosys0 and vdosys1 are 2 display HW pipelines,
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