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/Documentation/devicetree/bindings/media/i2c/
Dmipi-ccs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2014--2020 Intel Corporation
4 ---
5 $id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sakari Ailus <sakari.ailus@linux.intel.com>
17 <URL:https://www.mipi.org/specifications/camera-command-set>.
24 Documentation/devicetree/bindings/media/video-interfaces.txt .
29 - items:
30 - const: mipi-ccs-1.1
[all …]
Dmt9m111.txt4 array size of 1280H x 1024V. It is programmable through a simple two-wire serial
8 - compatible: value should be "micron,mt9m111"
9 - clocks: reference to the master clock.
10 - clock-names: shall be "mclk".
13 sub-node for its digital output video port, in accordance with the video
15 Documentation/devicetree/bindings/media/video-interfaces.txt
18 - pclk-sample: For information see ../video-interfaces.txt. The value is set to
28 clock-names = "mclk";
32 remote-endpoint = <&pxa_camera>;
33 pclk-sample = <1>;
Dtoshiba,et8ek8.txt6 Documentation/devicetree/bindings/media/video-interfaces.txt .
10 --------------------
12 - compatible: "toshiba,et8ek8"
13 - reg: I2C address (0x3e, or an alternative address)
14 - vana-supply: Analogue voltage supply (VANA), 2.8 volts
15 - clocks: External clock to the sensor
16 - clock-frequency: Frequency of the external clock to the sensor. Camera
18 a pre-determined frequency known to be suitable to the board.
19 - reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor
24 -------------------
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Dtvp514x.txt1 * Texas Instruments TVP514x video decoder
3 The TVP5146/TVP5146m2/TVP5147/TVP5147m1 device is high quality, single-chip
4 digital video decoder that digitizes and decodes all popular baseband analog
5 video formats into digital video component. The tvp514x decoder supports analog-
6 to-digital (A/D) conversion of component RGB and YPbPr signals as well as A/D
7 conversion and decoding of NTSC, PAL and SECAM composite and S-video into
11 - compatible : value should be either one among the following
17 - hsync-active: HSYNC Polarity configuration for endpoint.
19 - vsync-active: VSYNC Polarity configuration for endpoint.
21 - pclk-sample: Clock polarity of the endpoint.
[all …]
Dmaxim,max96714.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Maxim MAX96714 GMSL2 to CSI-2 Deserializer
11 - Julien Massot <julien.massot@collabora.com>
15 CSI-2 D-PHY formatted output. The device allows the GMSL2 link to
16 simultaneously transmit bidirectional control-channel data while forward
17 video transmissions are in progress. The MAX96714 can connect to one
18 remotely located serializer using industry-standard coax or STP
20 the MAX96714 can select individual video stream, while the tunnel mode forward all
[all …]
Dov7740.txt7 The common video interfaces bindings (see video-interfaces.txt) should
12 - compatible: "ovti,ov7740".
13 - reg: I2C slave address of the sensor.
14 - clocks: Reference to the xvclk input clock.
15 - clock-names: "xvclk".
18 - reset-gpios: Rreference to the GPIO connected to the reset_b pin,
19 if any. Active low with pull-ip resistor.
20 - powerdown-gpios: Reference to the GPIO connected to the pwdn pin,
21 if any. Active high with pull-down resistor.
24 - remote-endpoint: A phandle to the bus receiver's endpoint node.
[all …]
Dov9650.txt4 - compatible: shall be one of
7 - clocks: reference to the xvclk input clock.
10 - reset-gpios: reference to the GPIO connected to the resetb pin, if any.
12 - powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any.
16 subnode for its digital output video port, in accordance with the video
18 video-interfaces.txt.
26 reset-gpios = <&axi_gpio_0 0 GPIO_ACTIVE_HIGH>;
27 powerdown-gpios = <&axi_gpio_0 1 GPIO_ACTIVE_HIGH>;
32 remote-endpoint = <&vcap1_in0>;
Dovti,ov5642.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
13 - $ref: /schemas/media/video-interface-devices.yaml#
25 AVDD-supply:
28 DVDD-supply:
31 DOVDD-supply:
34 powerdown-gpios:
38 reset-gpios:
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Dthine,thp7312.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Elder <paul.elder@@ideasonboard.com>
17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
23 - $ref: /schemas/media/video-interface-devices.yaml#
36 thine,boot-mode:
43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
46 reset-gpios:
52 vddcore-supply:
[all …]
Dti,ds90ub960.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments DS90UB9XX Family FPD-Link Deserializer Hubs
10 - Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
13 The TI DS90UB9XX devices are FPD-Link video deserializers with I2C and GPIO
17 - $ref: /schemas/i2c/i2c-atr.yaml#
22 - ti,ds90ub960-q1
23 - ti,ds90ub9702-q1
33 clock-names:
[all …]
Dmt9m001.txt1 MT9M001: 1/2-Inch Megapixel Digital Image Sensor
3 The MT9M001 is an SXGA-format with a 1/2-inch CMOS active-pixel digital
8 - compatible: shall be "onnn,mt9m001".
9 - clocks: reference to the master clock into sensor
13 - reset-gpios: GPIO handle which is connected to the reset pin of the chip.
15 - standby-gpios: GPIO handle which is connected to the standby pin of the chip.
19 sub-node for its digital output video port, in accordance with the video
21 Documentation/devicetree/bindings/media/video-interfaces.txt
26 camera-sensor@5d {
29 reset-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
[all …]
Dovti,ov772x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo@jmondi.org>
20 - ovti,ov7720
21 - ovti,ov7725
29 reset-gpios:
34 powerdown-gpios:
40 $ref: /schemas/graph.yaml#/$defs/port-base
42 Video output port.
[all …]
/Documentation/userspace-api/media/v4l/
Ddv-timings.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _dv-timings:
6 Digital Video (DV) Timings
9 The video standards discussed so far have been dealing with Analog TV
10 and the corresponding video timings. Today there are many more different
11 hardware interfaces such as High Definition TV interfaces (HDMI), VGA,
12 DVI connectors etc., that carry video signals and there is a need to
13 extend the API to select the video timings for these interfaces. Since
14 it is not possible to extend the :ref:`v4l2_std_id <v4l2-std-id>`
16 set/get video timings at the input and output.
[all …]
/Documentation/devicetree/bindings/media/
Dvideo-interfaces.txt1 This file has moved to video-interfaces.yaml and video-interface-devices.yaml.
Dmarvell,mmp2-ccic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <lkundrak@v3.sk>
15 pattern: '^camera@[a-f0-9]+$'
18 const: marvell,mmp2-ccic
26 power-domains:
30 $ref: /schemas/graph.yaml#/$defs/port-base
35 $ref: video-interfaces.yaml#
[all …]
Dmicrochip,xisc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Eugen Hristev <eugen.hristev@microchip.com>
14 The eXtended Image Sensor Controller (XISC) device provides the video input capabilities for the
17 The XISC has a single internal parallel input that supports RAW Bayer, RGB or YUV video.
25 const: microchip,sama7g5-isc
36 clock-names:
38 - const: hclock
40 '#clock-cells':
[all …]
Dqcom,sm8250-camss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Robert Foss <robert.foss@linaro.org>
18 const: qcom,sm8250-camss
24 clock-names:
26 - const: cam_ahb_clk
27 - const: cam_hf_axi
28 - const: cam_sf_axi
[all …]
Dqcom,sdm660-camss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Robert Foss <robert.foss@linaro.org>
12 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
19 const: qcom,sdm660-camss
25 clock-names:
27 - const: ahb
28 - const: cphy_csid0
[all …]
Dqcom,msm8996-camss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Robert Foss <robert.foss@linaro.org>
12 - Todor Tomov <todor.too@gmail.com>
19 const: qcom,msm8996-camss
25 clock-names:
27 - const: top_ahb
28 - const: ispif_ahb
[all …]
/Documentation/devicetree/bindings/media/xilinx/
Dvideo.txt1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
6 creating a video pipeline.
8 Each video IP core is represented by an AMBA bus child node in the device
10 cores are represented as defined in ../video-interfaces.txt.
13 tree using bindings documented in ./xlnx,video.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
[all …]
Dxlnx,video.txt1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
[all …]
Dxlnx,v-tpg.txt1 Xilinx Video Test Pattern Generator (TPG)
2 -----------------------------------------
6 - compatible: Must contain at least one of
8 "xlnx,v-tpg-5.0" (TPG version 5.0)
9 "xlnx,v-tpg-6.0" (TPG version 6.0)
11 TPG versions backward-compatible with previous versions should list all
14 - reg: Physical base address and length of the registers set for the device.
16 - clocks: Reference to the video core clock.
18 - xlnx,video-format, xlnx,video-width: Video format and width, as defined in
19 video.txt.
[all …]
Dxlnx,v-tc.txt1 Xilinx Video Timing Controller (VTC)
2 ------------------------------------
4 The Video Timing Controller is a general purpose video timing generator and
9 - compatible: Must be "xlnx,v-tc-6.1".
11 - reg: Physical base address and length of the registers set for the device.
13 - clocks: Must contain a clock specifier for the VTC core and timing
14 interfaces clock.
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
28 compatible = "xlnx,v-tc-6.1";
/Documentation/devicetree/bindings/display/bridge/
Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
24 - ti,sn65dsi84
[all …]
/Documentation/firmware-guide/acpi/dsd/
Dleds.rst1 .. SPDX-License-Identifier: GPL-2.0
14 Referring to LEDs in Device tree is documented in [video-interfaces], in
15 "flash-leds" property documentation. In short, LEDs are directly referred to by
39 ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
46 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
49 Package () { "flash-max-microamp", 1000000 },
50 Package () { "flash-timeout-us", 200000 },
51 Package () { "led-max-microamp", 100000 },
56 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
59 Package () { "led-max-microamp", 10000 },
[all …]

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