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/Documentation/devicetree/bindings/regulator/
Dpwm-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
17 Voltage Table:
18 When in this mode, a voltage table (See below) of predefined voltage <=>
19 duty-cycle values must be provided via DT. Limitations are that the
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Drohm,bd71828-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/rohm,bd71828-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml.
16 The regulator controller is represented as a sub-node of the PMIC node
25 "^LDO[1-7]$":
32 regulator-name:
33 pattern: "^ldo[1-7]$"
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Drohm,bd71847-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/rohm,bd71847-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
15 Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml
21 regulator-boot-on at least for BUCK5. LDO6 is supplied by it and it must
23 voltage monitoring for LDO5/LDO6 can cause PMIC to reset.
30 "^LDO[1-6]$":
37 regulator-name:
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Drohm,bd71837-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/rohm,bd71837-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
15 Documentation/devicetree/bindings/mfd/rohm,bd71837-pmic.yaml
21 regulator-boot-on at least for BUCK6 and BUCK7 so that those are not
23 if they are disabled at startup the voltage monitoring for LDO5/LDO6 will
31 "^LDO[1-7]$":
38 regulator-name:
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/Documentation/devicetree/bindings/power/supply/
Dbattery.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
14 In smart batteries, these are typically stored in non-volatile memory
16 no appropriate non-volatile memory, or it is unprogrammed/incorrect.
27 Batteries must be referenced by chargers and/or fuel-gauges using a phandle.
28 The phandle's property should be named "monitored-battery".
32 const: simple-battery
34 device-chemistry:
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/Documentation/devicetree/bindings/thermal/
Dgeneric-adc-thermal.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/thermal/generic-adc-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laxman Dewangan <ldewangan@nvidia.com>
14 one of ADC channel and sensor resistance is read via voltage across the
15 sensor resistor. The voltage read across the sensor is mapped to
16 temperature using voltage-temperature lookup table.
18 $ref: thermal-sensor.yaml#
22 const: generic-adc-thermal
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/Documentation/userspace-api/media/cec/
Dcec-ioc-dqevent.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 CEC_DQEVENT - Dequeue a CEC event
35 non-blocking mode and no event is pending, then it will return -1 and
38 The internal event queues are per-filehandle and per-event type. If
43 two :ref:`CEC_EVENT_STATE_CHANGE <CEC-EVENT-STATE-CHANGE>` events with
51 .. flat-table:: struct cec_event_state_change
52 :header-rows: 0
53 :stub-columns: 0
56 * - __u16
57 - ``phys_addr``
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/Documentation/devicetree/bindings/opp/
Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
25 pattern: '^opp-table(-[a-z0-9]+)?$'
27 opp-shared:
29 Indicates that device nodes using this OPP Table Node's phandle switch
30 their DVFS state together, i.e. they share clock/voltage/current lines.
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Dallwinner,sun50i-h6-operating-points.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 For some SoCs, the CPU frequency subset and voltage value of each
16 Voltage Scaling Tables define the voltage and frequency values based
20 - $ref: opp-v2-base.yaml#
25 - allwinner,sun50i-h6-operating-points
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Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
13 - $ref: opp-v2-base.yaml#
17 the CPU frequencies subset and voltage value of each OPP varies based on
19 Qualcomm Technologies, Inc. Process Voltage Scaling Tables
20 defines the voltage and frequency value based on the speedbin blown in
22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
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/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-dfll.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
8 oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
9 control module that will automatically adjust the VDD_CPU voltage by
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
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/Documentation/devicetree/bindings/interconnect/
Dmediatek,cci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
10 - Jia-Wei Chang <jia-wei.chang@mediatek.com>
11 - Johnson Wang <johnson.wang@mediatek.com>
15 MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
16 hardware. It can also optimize the voltage to reduce the power consumption.
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
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/Documentation/devicetree/bindings/sound/
Dfsl,sgtl5000.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
13 - $ref: dai-common.yaml#
22 "#sound-dai-cells":
25 assigned-clock-parents: true
26 assigned-clock-rates: true
27 assigned-clocks: true
31 - description: the clock provider of SYS_MCLK
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/Documentation/hwmon/
Dtwl4030-madc-hwmon.rst1 Kernel driver twl4030-madc
8 Prefix: 'twl4030-madc'
12 J Keerthy <j-keerthy@ti.com>
15 -----------
18 other things it contains a 10-bit A/D converter MADC. The converter has 16
22 See this table for the meaning of the different channels
35 8 BCI: VBUS voltage(VBUS)
36 9 Backup Battery voltage (VBKP)
38 11 BCI: Battery charger voltage (VCHG)
39 12 BCI: Main battery voltage (VBAT)
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Dltc4245.rst10 Addresses scanned: 0x20-0x3f
20 -----------
28 -----------
38 $ echo ltc4245 0x23 > /sys/bus/i2c/devices/i2c-1/new_device
42 -------------
44 The LTC4245 has built-in limits for over and under current warnings. This
48 into the values specified in the sysfs-interface document. The current readings
49 rely on the sense resistors listed in Table 2: "Sense Resistor Values".
52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
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/Documentation/devicetree/bindings/power/avs/
Dqcom,cpr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <nks@flawful.org>
17 temperature, etc. and suggests adjustments to the voltage to save power
23 - enum:
24 - qcom,qcs404-cpr
25 - const: qcom,cpr
36 - description: Reference clock.
38 clock-names:
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/Documentation/devicetree/bindings/hwmon/
Dti,tmp513.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Eric Tremblay <etremblay@distech-controls.com>
14 The TMP512 (dual-channel) and TMP513 (triple-channel) are system monitors
15 that include remote sensors, a local temperature sensor, and a high-side
17 remote temperatures, on-chip temperatures, and system voltage/power/current
28 - ti,tmp512
29 - ti,tmp513
34 shunt-resistor-micro-ohms:
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Dntc-thermistor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 ---
3 $id: http://devicetree.org/schemas/hwmon/ntc-thermistor.yaml#
4 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Linus Walleij <linus.walleij@linaro.org>
13 vary in resistance in an often non-linear way in relation to temperature.
16 temperature is non-linear, software drivers most often need to use a look
17 up table and interpolation to get from resistance to temperature.
20 pull-up resistor or/and a pull-down resistor and a fixed voltage like this:
22 + e.g. 5V = pull-up voltage (puv)
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/Documentation/devicetree/bindings/ufs/
Dufs-common.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/ufs-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
11 - Avri Altman <avri.altman@wdc.com>
16 clock-names: true
18 freq-table-hz:
21 - description: Minimum frequency for given clock in Hz
22 - description: Maximum frequency for given clock in Hz
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/Documentation/userspace-api/media/v4l/
Dext-ctrls-flash.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _flash-controls:
17 .. _flash-controls-use-cases:
24 ------------------------------------------
35 ----------------------------------------
37 The synchronised LED flash is pre-programmed by the host (power and
46 ------------------
52 .. _flash-control-id:
55 -----------------
61 Defines the mode of the flash LED, the high-power white LED attached
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/Documentation/power/regulator/
Doverview.rst2 Linux voltage and current regulator framework
9 voltage and current regulators.
12 in order to save power and prolong battery life. This applies to both voltage
13 regulators (where voltage output is controllable) and current sinks (where
26 - Regulator
27 - Electronic device that supplies power to other devices.
29 some can control their output voltage and or current.
31 Input Voltage -> Regulator -> Output Voltage
34 - PMIC
35 - Power Management IC. An IC that contains numerous
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/Documentation/devicetree/bindings/cpufreq/
Dqcom-cpufreq-nvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ilia Lin <ilia.lin@kernel.org>
14 voltage is dynamically configured by Core Power Reduction (CPR) depending on
20 For old implementation efuses are parsed to select the correct opp table and
21 voltage and CPR is not supported/used.
28 - qcom,apq8064
29 - qcom,apq8096
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/Documentation/driver-api/thermal/
Dintel_dptf.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ------------
31 ----------------------------
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
47 "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical
49 "63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance
51 "5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call
53 "9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2
55 "F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Boss
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/Documentation/devicetree/bindings/gpu/
Darm,mali-valhall-csf.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-valhall-csf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liviu Dudau <liviu.dudau@arm.com>
11 - Boris Brezillon <boris.brezillon@collabora.com>
15 pattern: '^gpu@[a-f0-9]+$'
19 - items:
20 - enum:
21 - rockchip,rk3588-mali
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/Documentation/power/
Dopp.rst5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
26 domains to run at lower voltage and frequency while other domains run at
27 voltage/frequency pairs that are higher.
29 The set of discrete tuples consisting of frequency and voltage pairs that
36 {300MHz at minimum voltage of 1V}, {800MHz at minimum voltage of 1.2V},
37 {1GHz at minimum voltage of 1.3V}
41 - {300000000, 1000000}
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