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/Documentation/devicetree/bindings/regulator/
Drichtek,rtmv20-regulator.yaml16 There're still four pins for camera control, two inputs (strobe and vsync),
18 supply, vsync input from IR camera, and fsin1/fsin2 output for the optional.
52 Fsin1 pulse high delay in microsecond after vsync signal pulse high.
59 Fsin1 pulse high width in microsecond after vsync signal pulse high.
66 Fsin2 pulse high delay in microsecond after vsync signal pulse high.
73 Fsin2 pulse high width in microsecond after vsync signal pulse high.
104 richtek,vsync-polarity-high:
105 description: Vsync pin active polarity control.
151 richtek,vsync-polarity-high;
/Documentation/devicetree/bindings/media/i2c/
Dtvp514x.txt19 - vsync-active: VSYNC Polarity configuration for endpoint.
38 vsync-active = <1>;
Dtvp7002.txt13 - vsync-active: VSYNC Polarity configuration for the bus. Default value when
45 vsync-active = <1>;
Dov7670.txt14 - vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
49 vsync-active = <0>;
Dovti,ov772x.yaml65 vsync-active:
81 vsync-active: false
123 vsync-active = <0>;
Dovti,ov5642.yaml68 vsync-active:
84 vsync-active: false
136 vsync-active = <0>;
/Documentation/fb/
Dviafb.modes202 timings 25000 88 40 23 1 128 4 hsync high vsync high endmode
224 timings 20203 160 16 21 1 80 3 hsync high vsync high endmode
246 timings 17777 152 32 27 1 64 3 hsync high vsync high endmode
268 timings 14667 216 0 14 7 64 4 hsync high vsync high endmode
290 timings 11912 144 56 39 1 88 3 hsync high vsync high endmode
312 timings 31746 104 24 12 3 80 5 hsync high vsync high endmode
335 hsync high vsync high endmode mode "960x600-60"
389 timings 24218 126 32 15 1 104 3 hsync high vsync high endmode
455 timings 12699 176 16 28 1 96 3 hsync high vsync high endmode
477 timings 10582 208 48 36 1 96 3 hsync high vsync high endmode
[all …]
/Documentation/admin-guide/media/
Dmgb4.rst98 The type of VSYNC pulses as detected by the video format detector.
118 If the incoming video signal does not contain synchronization VSYNC and
122 internal VSYNC pulse.
125 If the incoming video signal does not contain synchronization VSYNC and
148 Width of the VSYNC signal in PCLK clock ticks.
151 the vsync field of the v4l2_bt_timings struct.
168 Number of video lines between deassertion of the VSYNC signal and the video
176 by DE=1) and assertion of the VSYNC signal.
245 VSYNC signal polarity.
270 Width of the VSYNC signal in video lines. The default value is 20.
[all …]
/Documentation/devicetree/bindings/display/msm/
Dqcom,qcm2290-dpu.yaml34 - description: Display vsync clock from dispcc
42 - const: vsync
70 clock-names = "bus", "iface", "core", "lut", "vsync";
Dqcom,sm6115-dpu.yaml35 - description: Display vsync
44 - const: vsync
73 clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
Dqcom,sdm845-dpu.yaml36 - description: Display vsync clock
44 - const: vsync
72 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
Dqcom,sm8150-dpu.yaml33 - description: Display vsync clock
40 - const: vsync
62 clock-names = "iface", "bus", "core", "vsync";
Dqcom,sc7280-dpu.yaml35 - description: Display vsync clock
44 - const: vsync
79 "vsync";
Dqcom,sm8250-dpu.yaml33 - description: Display vsync clock
40 - const: vsync
69 clock-names = "iface", "bus", "core", "vsync";
Dqcom,msm8998-dpu.yaml38 - description: Display vsync clock
46 - const: vsync
75 clock-names = "iface", "bus", "mnoc", "core", "vsync";
Dqcom,sc7180-dpu.yaml40 - description: Display vsync clock
51 - const: vsync
99 "vsync";
Dqcom,sc8280xp-dpu.yaml38 - description: Display vsync clock
47 - const: vsync
76 "vsync";
Dqcom,sm8350-dpu.yaml35 - description: Display vsync clock
44 - const: vsync
73 "vsync";
Dqcom,sm8650-dpu.yaml36 - description: Display vsync
44 - const: vsync
75 "vsync";
Dqcom,sm8550-dpu.yaml35 - description: Display vsync
44 - const: vsync
79 "vsync";
Dqcom,mdss.yaml55 - description: Display vsync clock
68 - const: vsync
171 "vsync";
197 "vsync";
Dqcom,sm7150-dpu.yaml35 - description: Display vsync clock
44 - const: vsync
77 "vsync";
/Documentation/devicetree/bindings/media/
Dallwinner,sun4i-a10-csi.yaml86 vsync-active: true
93 - vsync-active
122 vsync-active = <0>; /* Active low */
Drenesas,vin.yaml92 If both HSYNC and VSYNC polarities are not specified, embedded
96 vsync-active:
98 If both HSYNC and VSYNC polarities are not specified, embedded
141 If both HSYNC and VSYNC polarities are not specified, embedded
145 vsync-active:
147 If both HSYNC and VSYNC polarities are not specified, embedded
345 vsync-active = <0>;
/Documentation/devicetree/bindings/display/samsung/
Dsamsung,exynos7-decon.yaml72 - description: VSYNC
78 - const: vsync
105 interrupt-names = "fifo", "vsync", "lcd_sys";

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