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/Documentation/devicetree/bindings/cpu/
Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/Documentation/tools/rtla/
Drtla-timerlat-top.rst2 rtla-timerlat-top
4 -------------------------------------------
5 Measures the operating system timer latency
6 -------------------------------------------
22 seem with the option **-T**.
35 **--aa-only** *us*
38 Print the auto-analysis if the system hits the stop tracing condition. This option
45 In the example below, the timerlat tracer is dispatched in cpus *1-23* in the
46 automatic trace mode, instructing the tracer to stop if a *40 us* latency or
49 # timerlat -a 40 -c 1-23 -q
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/Documentation/trace/
Dftrace.rst2 ftrace - Function Tracer
13 - Written for: 2.6.28-rc2
14 - Updated for: 3.10
15 - Updated for: 4.13 - Copyright 2017 VMware Inc. Steven Rostedt
16 - Converted to rst format - Changbin Du <changbin.du@intel.com>
19 ------------
24 performance issues that take place outside of user-space.
28 There's latency tracing to examine what occurs between interrupts
41 ----------------------
43 See Documentation/trace/ftrace-design.rst for details for arch porters and such.
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Dtimerlat-tracer.rst6 find sources of wakeup latencies of real-time threads. Like cyclictest,
8 computes a *wakeup latency* value as the difference between the *current
13 -----
28 # _-----=> irqs-off
29 # / _----=> need-resched
30 # | / _---=> hardirq/softirq
31 # || / _--=> preempt-depth
34 # TASK-PID CPU# |||| TIMESTAMP ID CONTEXT LATENCY
36 <idle>-0 [000] d.h1 54.029328: #1 context irq timer_latency 932 ns
37 <...>-867 [000] .... 54.029339: #1 context thread timer_latency 11700 ns
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Dhistogram.rst33 numeric fields - on an event hit, the value(s) will be added to a
35 in place of an explicit value field - this is simply a count of
45 useful for providing more fine-grained summaries of event data.
69 numeric fields are displayed as base-10 integers. This can be
76 .sym-offset display an address as a symbol and offset
83 .graph display a bar-graph of a value
91 - only the 'hex' modifier can be used for values (because values
94 - the 'execname' modifier can only be used on a 'common_pid'. The
100 pid-specific comm fields in the event itself.
119 are in terms of hashtable entries - if a run uses more entries than
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/Documentation/virt/kvm/
Dhalt-polling.rst1 .. SPDX-License-Identifier: GPL-2.0
7 The KVM halt polling system provides a feature within KVM whereby the latency
11 vcpus of a single vcore have ceded, the host kernel polls for wakeup conditions
14 Polling provides a latency advantage in cases where the guest can be run again
15 very quickly by at least saving us a trip through the scheduler, normally on
16 the order of a few micro-seconds, although performance benefits are workload
17 dependent. In the event that no wakeup source arrives during the polling
20 wakeup periods where the time spent halt polling is minimised and the time
27 The powerpc kvm-hv specific case is implemented in:
39 kvm_vcpu->halt_poll_ns
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/Documentation/driver-api/thermal/
Dcpu-idle-cooling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
58 ---------------
67 latencies as the CPUs will have to wakeup from a deep sleep state.
70 performance penalty and a fixed latency. Mitigation can be increased
78 |------- -------
81 <------>
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/Documentation/accounting/
Dpsi.rst4 PSI - Pressure Stall Information
11 latency spikes, throughput losses, and run the risk of OOM kills.
14 either play it safe and under-utilize their hardware resources, or
23 scarcity aids users in sizing workloads to hardware--or provisioning
38 respective file in /proc/pressure/ -- cpu, memory, and io.
48 The "full" line indicates the share of time in which all non-idle
63 (in us) is tracked and exported as well, to allow detection of latency
75 generate a wakeup event.
83 <some|full> <stall amount in us> <time window in us>
116 Notifications to the userspace are rate-limited to one per tracking window.
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/Documentation/admin-guide/pm/
Dintel_idle.rst1 .. SPDX-License-Identifier: GPL-2.0
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
28 processor's functional blocks into low-power states. That instruction takes two
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
50 as C-states (in the ACPI terminology) or idle states. The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
56 subsystem (see :ref:`idle-states-representation` in
57 Documentation/admin-guide/pm/cpuidle.rst),
66 `below <intel-idle-parameters_>`_.]
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Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
49 The top-level help describes arguments and features. Notice that there is a
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/Documentation/gpu/rfc/
Di915_vm_bind.rst18 User has to opt-in for VM_BIND mode of binding for an address space (VM)
34 ------------------------
42 -------------------------------
52 "dma-buf: Add an API for exporting sync files"
68 be using the i915_vma active reference tracking. It will instead use dma-resv
78 -------------------
79 By default, BOs can be mapped on multiple VMs and can also be dma-buf
82 dma-resv fence list of all shared BOs mapped on the VM.
87 the VM they are private to and can't be dma-buf exported.
88 All private BOs of a VM share the dma-resv object. Hence during each execbuf
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/Documentation/scheduler/
Dsched-util-clamp.rst1 .. SPDX-License-Identifier: GPL-2.0
57 foreground, top-app, etc. Util clamp can be used to constrain how much
60 the ones belonging to the currently active app (top-app group). Beside this
65 1. The big cores are free to run top-app tasks immediately. top-app
82 Another use case is to help with **overcoming the ramp up latency inherit in
106 Note that by design RT tasks don't have per-task PELT signal and must always
114 See :ref:`section 3.4 <uclamp-default-values>` for default values and
115 :ref:`3.4.1 <sched-util-clamp-min-rt-default>` on how to change RT tasks
134 level, which brings us to the main design challenge.
149 (struct uclamp_bucket) which allows us to reduce the search space from every
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