Searched +full:wire +full:- +full:or (Results 1 – 25 of 126) sorted by relevance
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| /Documentation/w1/masters/ |
| D | w1-uart.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 Kernel driver w1-uart
11 -----------
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 …g a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-a-u…
19 In short, the UART peripheral must support full-duplex and operate in
20 open-drain mode. The timing patterns are generated by a specific
21 combination of baud-rate and transmitted byte, which corresponds to a
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| /Documentation/devicetree/bindings/w1/ |
| D | w1-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/w1/w1-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART 1-Wire Bus
10 - Christoph Winklhofer <cj.winklhofer@gmail.com>
13 UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
14 to create the 1-Wire timing patterns.
16 The UART peripheral must support full-duplex and operate in open-drain
18 baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
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| D | amd,axi-1wire-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AMD AXI 1-wire bus host for programmable logic
10 - Kris Chaplin <kris.chaplin@amd.com>
14 const: amd,axi-1wire-host
26 - compatible
27 - reg
28 - clocks
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| D | omap-hdq.txt | 1 * OMAP HDQ One wire bus master controller
4 - compatible : should be "ti,omap3-1w" or "ti,am4372-hdq"
5 - reg : Address and length of the register set for the device
6 - interrupts : interrupt line.
7 - ti,hwmods : "hdq1w"
10 - ti,mode: should be "hdq": HDQ mode "1w": one-wire mode.
15 - From omap3.dtsi
17 compatible = "ti,omap3-1w";
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| D | maxim,ds2482.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Maxim One wire bus master controller
10 - Stefan Wahren <stefan.wahren@chargebyte.com>
13 I2C to 1-wire bridges
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ds2482-100.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/DS2482-800.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/DS2484.pdf
22 - maxim,ds2482
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| /Documentation/devicetree/bindings/iio/temperature/ |
| D | maxim,max31865.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Navin Sankar Velliangiri <navin@linumiz.com>
22 maxim,3-wire:
25 enables 3-wire RTD connection. Else 2-wire or 4-wire RTD connection.
28 spi-cpha: true
31 - compatible
32 - reg
33 - spi-cpha
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| /Documentation/peci/ |
| D | peci.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
13 controller is acting as a PECI originator and the processor - as
15 PECI can be used in both single processor and multiple-processor based
24 PECI Wire
25 ---------
27 PECI Wire interface uses a single wire for self-clocking and data
28 transfer. It does not require any additional control lines - the
29 physical layer is a self-clocked one-wire bus signal that begins each
32 value is logic '0' or logic '1'. PECI Wire also includes variable data
35 For PECI Wire, each processor package will utilize unique, fixed
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | intel,ce4100-lapic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
28 [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
32 const: intel,ce4100-lapic
37 interrupt-controller: true
39 '#interrupt-cells':
42 intel,virtual-wire-mode:
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| /Documentation/devicetree/bindings/display/panel/ |
| D | tpo,tpg110.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Thierry Reding <thierry.reding@gmail.com>
17 and other properties, and has a control interface over 3WIRE
20 self-describing.
22 +--------+
23 SPI -> | TPO | -> physical display
24 RGB -> | TPG110 |
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| D | leadtek,ltk035c5444t.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Leadtek ltk035c5444t 3.5" (640x480 pixels) 24-bit IPS LCD panel
10 - Paul Cercueil <paul@crapouillou.net>
11 - Christophe Branchereau <cbranchereau@gmail.com>
14 - $ref: panel-common.yaml#
15 - $ref: /schemas/spi/spi-peripheral-props.yaml#
24 spi-3wire: true
27 - compatible
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| D | fascontek,fs035vg158.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Fascontek FS035VG158 3.5" (640x480 pixels) 24-bit IPS LCD panel
10 - John Watts <contact@jookia.org>
13 - $ref: panel-common.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
23 spi-3wire: true
26 - compatible
27 - reg
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| D | anbernic,rg35xx-plus-panel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/anbernic,rg35xx-plus-panel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Anbernic RG35XX series (WL-355608-A8) 3.5" 640x480 24-bit IPS LCD panel
10 - Ryan Walklin <ryan@testtoast.com>
13 - $ref: panel-common.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
19 - const: anbernic,rg35xx-plus-panel
20 - items:
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| D | ilitek,ili9341.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ilitek-9341 Display Panel
10 - Dillon Min <dillon.minfei@gmail.com>
15 streams with 16 bits or 18 bits.
18 - $ref: panel-common.yaml#
19 - $ref: /schemas/spi/spi-peripheral-props.yaml#
24 - enum:
25 - adafruit,yx240qv29
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| /Documentation/devicetree/bindings/sound/ |
| D | awinic,aw8738.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
14 (set using one-wire pulse control). The mode configures the speaker-guard
18 - $ref: dai-common.yaml#
24 mode-gpios:
26 GPIO used for one-wire pulse control. The pin is typically called SHDN
27 (active-low), but this is misleading since it is actually more than
32 description: Operation mode (number of pulses for one-wire pulse control)
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| D | mediatek,mt8365-afe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mediatek,mt8365-afe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Mergnat <amergnat@baylibre.com>
14 const: mediatek,mt8365-afe-pcm
19 "#sound-dai-cells":
24 - description: 26M clock
25 - description: mux for audio clock
26 - description: audio i2s0 mck
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | ti,am3359-tsc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/touchscreen/ti,am3359-tsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 const: ti,am3359-tsc
17 description: Wires refer to application modes i.e. 4/5/8 wire touchscreen
22 ti,x-plate-resistance:
26 ti,coordinate-readouts:
36 ti,wire-config:
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| /Documentation/devicetree/bindings/leds/backlight/ |
| D | kinetic,ktd253.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Kinetic Technologies KTD253 and KTD259 one-wire backlight
10 - Linus Walleij <linus.walleij@linaro.org>
16 using pulses on the enable wire. This is sometimes referred to as
20 - $ref: common.yaml#
25 - enum:
26 - kinetic,ktd253
27 - kinetic,ktd259
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| /Documentation/driver-api/gpio/ |
| D | intro.rst | 17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
20 represents a bit connected to a particular pin, or "ball" on Ball Grid Array
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
30 also "GPIO Expander" chips that connect using the I2C or SPI serial buses.
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad7944.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <Michael.Hennerich@analog.com>
11 - Nuno Sá <nuno.sa@analog.com>
14 A family of pin-compatible single channel differential analog to digital
21 $ref: /schemas/spi/spi-peripheral-props.yaml#
26 - adi,ad7944
27 - adi,ad7985
28 - adi,ad7986
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| /Documentation/sound/soc/ |
| D | dai.rst | 12 AC97 is a five wire interface commonly found on many PC sound cards. It is
26 I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
35 I2S has several different operating modes:-
50 PCM is another 4 wire interface, very similar to I2S, which can support a more
58 Common PCM operating modes:-
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| /Documentation/w1/ |
| D | w1-generic.rst | 2 Introduction to the 1-wire (w1) subsystem
5 The 1-wire bus is a simple master-slave bus that communicates via a single
6 signal wire (plus ground, so two wires).
18 - DS9490 usb device
19 - W1-over-GPIO
20 - DS2482 (i2c to w1 bridge)
21 - Emulated devices, such as a RS232 converter, parallel port adapter, etc
25 ------------------------------
29 - sysfs entries for that w1 master are created
30 - the w1 bus is periodically searched for new slave devices
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| /Documentation/netlink/specs/ |
| D | netdev.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
9 -
11 name: xdp-act
12 render-max: true
14 -
19 -
23 -
24 name: ndo-xmit
27 -
28 name: xsk-zerocopy
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| /Documentation/hwmon/ |
| D | adt7411.rst | 17 -----------
22 The ADT7411 can use an I2C/SMBus compatible 2-wire interface or an
23 SPI-compatible 4-wire interface. It provides a 10-bit analog to digital
26 loses 2 inputs then). There are high- and low-limit registers for all inputs.
30 sysfs-Interface
31 ---------------
35 in[1-8]_input analog 1-8 input
48 -----
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| /Documentation/devicetree/bindings/clock/ |
| D | ti,lmk04832.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Beguin <liambeguin@gmail.com>
21 - ti,lmk04832
26 '#address-cells':
29 '#size-cells':
32 '#clock-cells':
35 spi-max-frequency:
40 - description: PLL2 reference clock.
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| /Documentation/devicetree/bindings/iio/addac/ |
| D | adi,ad74115.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
25 - adi,ad74115h
30 spi-max-frequency:
33 spi-cpol: true
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