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/Documentation/devicetree/bindings/mmc/
Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
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Dpxa-mmc.txt6 - compatible: Should be "marvell,pxa-mmc".
7 - vmmc-supply: A regulator for VMMC
10 - marvell,detect-delay-ms: sets the detection delay timeout in ms.
18 compatible = "marvell,pxa-mmc";
21 vmmc-supply = <&mmc_regulator>;
22 cd-gpios = <&gpio 23 0>;
23 wp-gpios = <&gpio 24 0>;
Dk3-dw-mshc.txt4 Read synopsys-dw-mshc.txt for more details
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
22 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
30 compatible = "hisilicon,hi4511-dw-mshc";
33 #address-cells = <1>;
34 #size-cells = <0>;
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Datmel-hsmci.txt7 by mmc.txt and the properties used by the atmel-mci driver.
12 - compatible: should be "atmel,hsmci"
13 - #address-cells: should be one. The cell is the slot id.
14 - #size-cells: should be zero.
15 - at least one slot node
16 - clock-names: tuple listing input clock names.
18 - clocks: phandles to input clocks.
28 #address-cells = <1>;
29 #size-cells = <0>;
30 clock-names = "mci_clk";
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Dfsl-imx-esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
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Dnvidia,tegra20-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 mmc-controller.yaml and the properties for the Tegra SDHCI controller.
23 - enum:
24 - nvidia,tegra20-sdhci
25 - nvidia,tegra30-sdhci
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/Documentation/devicetree/bindings/pinctrl/
Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
23 uart1(cts), lcd-spi(cs1), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
35 mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
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Drenesas,rzg2l-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
24 - items:
25 - enum:
26 - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
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/Documentation/devicetree/bindings/mtd/
Djedec,spi-nor.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: mtd.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
19 - items:
20 - pattern: "^((((micron|spansion|st),)?\
33 - const: jedec,spi-nor
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Dnvidia-tegra20-nand.txt4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
14 - reset-names: Must include the following entries:
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Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
14 - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
25 - description: Bank number, offset and size of first attached NAND chip
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Draw-nand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
32 Contains the chip-select IDs.
34 nand-ecc-placement:
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/Documentation/devicetree/bindings/iio/potentiometer/
Drenesas,x9250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
18 - $ref: /schemas/spi/spi-peripheral-props.yaml
23 - renesas,x9250t
24 - renesas,x9250u
29 vcc-supply:
33 avp-supply:
37 avn-supply:
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/Documentation/devicetree/bindings/nvmem/
Dnvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
23 "#address-cells":
26 "#size-cells":
29 read-only:
34 wp-gpios:
36 GPIO to which the write-protect pin of the chip is connected.
37 The write-protect GPIO is asserted, when it's driven high
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/Documentation/devicetree/bindings/eeprom/
Dat25.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Eggers <ceggers@arri.de>
15 - pattern: "^eeprom@[0-9a-f]{1,2}$"
16 - pattern: "^fram@[0-9a-f]{1,2}$"
26 - items:
27 - enum:
28 - anvo,anv32e61w
29 - atmel,at25256B
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Dat24.yaml1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
14 - $ref: /schemas/nvmem/nvmem.yaml
15 - $ref: /schemas/nvmem/nvmem-deprecated-cells.yaml
22 - pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
23 - enum: ["microchip,24aa025e48", "microchip,24aa025e64"]
25 - compatible
29 pattern: "^eeprom@[0-9a-f]{1,2}$"
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/Documentation/devicetree/bindings/display/ti/
Dti,omap-dss.txt5 -------------------
25 -----------
36 -------
39 name for each display. If no aliases are defined, a semi-random number is used
43 -------
45 A shortened example of the DSS description for OMAP4, with non-relevant parts
49 compatible = "ti,omap4-dss";
54 clock-names = "fck";
55 #address-cells = <1>;
56 #size-cells = <1>;
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/Documentation/devicetree/bindings/gpio/
Dgpio.txt4 1) gpios property
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
9 for compatibility reasons (resolving to the "gpios" property), it is not allowed
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
15 cases should they contain more than one. If your device uses several GPIOs with
17 meaningful name. The only case where an array of GPIOs is accepted is when
18 several GPIOs serve the same function (e.g. a parallel data line).
20 The exact purpose of each gpios property must be documented in the device tree
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