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/Documentation/devicetree/bindings/memory-controllers/
Darm,pl172.txt5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
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Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
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Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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/Documentation/ABI/testing/
Dsysfs-driver-xdata1 What: /sys/class/misc/drivers/dw-xdata-pcie.<device>/write
5 Description: Allows the user to enable the PCIe traffic generator which
6 will create write TLPs frames - from the Root Complex to the
10 Write y/1/on to enable, n/0/off to disable
13 echo 1 > /sys/class/misc/dw-xdata-pcie.<device>/write
15 echo 0 > /sys/class/misc/dw-xdata-pcie.<device>/write
21 cat /sys/class/misc/dw-xdata-pcie.<device>/write
24 The file is read and write.
26 What: /sys/class/misc/dw-xdata-pcie.<device>/read
30 Description: Allows the user to enable the PCIe traffic generator which
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Dsysfs-bus-iio-dac-ad57663 Contact: linux-iio@vger.kernel.org
5 Dither enable. Write 1 to enable dither or 0 to disable it.
9 Contact: linux-iio@vger.kernel.org
12 inverted by default. Write "1" to invert dither.
16 Contact: linux-iio@vger.kernel.org
22 Contact: linux-iio@vger.kernel.org
28 Contact: linux-iio@vger.kernel.org
30 Selects dither source applied to the selected channel. Write "0" to
31 select N0 source, write "1" to select N1 source.
Dsysfs-bus-iio-adc-mcp35643 Contact: linux-iio@vger.kernel.org
6 circuit of the Delta-Sigma modulator. The different BOOST
12 Contact: linux-iio@vger.kernel.org
15 the current biasing circuit of the Delta-Sigma modulator.
19 Contact: linux-iio@vger.kernel.org
21 This attribute is used to enable the analog input multiplexer
22 auto-zeroing algorithm (the input multiplexer and the ADC
26 input as VIN+/VIN-, one with VIN+/VIN- inverted. In this case the
30 ultra-low offset without any digital calibration. The resulting
35 Write '1' to enable it, write '0' to disable it.
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Dsysfs-platform-dell-laptop9 light sensor. Write 1 to this file to enable the auto
31 enabled are preceded by '+', those disabled by '-'.
33 To enable a trigger, write its name preceded by '+' to
34 this file. To disable a trigger, write its name preceded
35 by '-' instead.
37 For example, to enable the keyboard as trigger run::
43 echo -keyboard > /sys/class/leds/dell::kbd_backlight/start_triggers
59 To configure the timeout, write to this file a value along
Dsysfs-bus-iio-dac3 Contact: linux-iio@vger.kernel.org
5 Toggle enable. Write 1 to enable toggle or 0 to disable it. This
9 - disable toggle operation;
10 - change out_currentY_rawN, where N is the integer value of the symbol;
11 - enable toggle operation.
15 Contact: linux-iio@vger.kernel.org
24 Contact: linux-iio@vger.kernel.org
34 Contact: linux-iio@vger.kernel.org
36 Toggle enable. Write 1 to enable toggle or 0 to disable it. This
40 - disable toggle operation;
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Dsysfs-bus-coresight-devices-cti1 What: /sys/bus/coresight/devices/<cti-name>/enable
5 Description: (RW) Enable/Disable the CTI hardware.
7 What: /sys/bus/coresight/devices/<cti-name>/powered
13 What: /sys/bus/coresight/devices/<cti-name>/ctmid
19 What: /sys/bus/coresight/devices/<cti-name>/nr_trigger_cons
25 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/name
31 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_signals
37 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_types
44 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_signals
50 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/out_types
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Dsysfs-ptp41 Write integer to re-configure it.
110 This write-only file enables or disables external
111 timestamps. To enable external timestamps, write the
113 To disable external timestamps, write the channel
128 This write-only file enables or disables periodic
129 outputs. To enable a periodic output, write five
139 This write-only file enables or disables delivery of
140 PPS events to the Linux PPS subsystem. To enable PPS
141 events, write a "1" into the file. To disable events,
142 write a "0" into the file.
Ddebugfs-driver-dcc27 What: /sys/kernel/debug/dcc/.../[list-number]/config
35 write, read-write, and loop type. The lists need to
45 echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config
61 ii) Write instruction
65 echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config
78 iii) Read-write instruction
82 echo RW <addr> <n> <mask> > /sys/kernel/debug/dcc/../[list-number]/config
99 … echo L <loop count> <address count> <address>... > /sys/kernel/debug/dcc/../[list-number]/config
110 Space-separated list of addresses.
112 What: /sys/kernel/debug/dcc/.../[list-number]/enable
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Dconfigfs-spear-pcie-gadget1 What: /config/pcie-gadget
15 # mount -t configfs none /config/
17 For nth PCIe Device Controller /config/pcie-gadget.n/:
20 link used to enable ltssm and read its status.
24 inta write 1 to assert INTA and 0 to de-assert.
25 send_msi write MSI vector to be sent.
26 vendor_id used to write and read vendor id (hex)
27 device_id used to write and read device id (hex)
28 bar0_size used to write and read bar0_size
29 bar0_address used to write and read bar0 mapped area in hex.
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Dsysfs-firmware-acpi29 OS write to SLP_TYP upon entry to S3. In
32 firmware write to SLP_TYP used to trigger
55 image: The image bitmap. Currently a 32-bit BMP.
92 or 0 (unset). Attempts to write any other values to it will
93 cause -EINVAL to be returned.
127 ff_gbl_lock: 0 enable
129 ff_pwr_btn: 0 enable
133 gpe01: 0 enable
134 gpe02: 108 enable
138 gpe06: 0 enable
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/Documentation/devicetree/bindings/cache/
Dl2c2x0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
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/Documentation/driver-api/mmc/
Dmmc-tools.rst5 There is one MMC test tools called mmc-utils, which is maintained by Ulf Hansson,
8 https://git.kernel.org/pub/scm/utils/mmc/mmc-utils.git
13 The mmc-utils tools can do the following:
15 - Print and parse extcsd data.
16 - Determine the eMMC writeprotect status.
17 - Set the eMMC writeprotect status.
18 - Set the eMMC data sector size to 4KB by disabling emulation.
19 - Create general purpose partition.
20 - Enable the enhanced user area.
21 - Enable write reliability per partition.
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Dmmc-dev-parts.rst15 Read and write access is provided to the two MMC boot partitions. Due to
18 platform, write access is disabled by default to reduce the chance of
21 To enable write access to /dev/mmcblkXbootY, disable the forced read-only
26 To re-enable read-only access::
37 feature has been disabled on the card, the file will be read-only.
/Documentation/devicetree/bindings/serio/
Dps2-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serio/ps2-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Danilo Krummrich <danilokrummrich@dk-develop.de>
14 const: ps2-gpio
16 data-gpios:
18 the gpio used for the data signal - this should be flagged as
20 from <dt-bindings/gpio/gpio.h> since the signal is open drain by
24 clk-gpios:
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/Documentation/PCI/
Dsysfs-pci.rst1 .. SPDX-License-Identifier: GPL-2.0
11 |-- 0000:17:00.0
12 | |-- class
13 | |-- config
14 | |-- device
15 | |-- enable
16 | |-- irq
17 | |-- local_cpus
18 | |-- remove
19 | |-- resource
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/Documentation/devicetree/bindings/bus/
Dqcom,ebi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 external memory (such as NAND or other memory-mapped peripherals) whereas
16 data lines (16 bits), OE (output enable), ADV (address valid, used on some
17 NOR flash memories), WE (write enable). This on top of 6 different chip selects
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
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/Documentation/devicetree/bindings/dma/
Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx
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/Documentation/scsi/
Dsd-parameters.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ---------------
9 Enable/disable drive write & read cache.
12 cache_type string WCE RCD Write cache Read cache
14 write through 0 0 off on
16 write back 1 0 on on
17 write back, no read (daft) 1 1 on off
20 To set cache type to "write back" and save this setting to the drive::
22 # echo "write back" > cache_type
27 # echo "temporary write back" > cache_type
/Documentation/hwmon/
Dltc4282.rst1 .. SPDX-License-Identifier: GPL-2.0-only
12 Addresses scanned: - I2C 0x40 - 0x5A (7-bit)
13 Addresses scanned: - I2C 0x80 - 0xB4 with a step of 2 (8-bit)
17 https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4282.pdf
25 from a live backplane. Using one or more external N-channel pass transistors,
31 parallel MOSFETs or support a 2-stage start-up that first charges the load
32 capacitance followed by enabling a low on-resistance path to the load. The
35 and power supplies must safely operate. Non-volatile configuration allows for
41 The following attributes are supported. Limits are read-write and all the other
42 attributes are read-only. Note that in0 and in1 are mutually exclusive. Enabling
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/Documentation/admin-guide/device-mapper/
Ddm-dust.rst1 dm-dust
5 locations, and the ability to enable the emulation of the failures
20 2. Successfully complete the write.
27 With dm-dust, the user can use the "addbadblock" and "removebadblock"
29 "enable" and "disable" messages to modulate the state of whether the
31 This allows the pre-writing of test data and metadata prior to
35 ----------------
51 ------------------
53 First, find the size (in 512-byte sectors) of the device to be used::
55 $ sudo blockdev --getsz /dev/vdb1
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/Documentation/driver-api/
Dpwm.rst15 ----------------
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
36 ----------
47 enable/disable state.
71 pwm_{enable,disable}() calls in the same function, this probably means you
82 PWM arguments are usually platform-specific and allows the PWM user to only
93 -----------------------------------
102 The number of PWM channels this chip supports (read-only).
105 Exports a PWM channel for use with sysfs (write-only).
108 Unexports a PWM channel from sysfs (write-only).
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/Documentation/w1/slaves/
Dw1_therm.rst16 -----------
49 -1 if at least one sensor still in conversion, 1 if conversion is complete
60 adjust it (write). A temperature conversion time depends on the device type and
66 ``conv_time``; 3) use ``features`` to enable poll for conversion
68 the default conversion time write ``0`` to ``conv_time``.
72 the sensor. Resolution is reset when the sensor gets power-cycled.
74 To store the current resolution in EEPROM, write ``0`` to ``w1_slave``.
81 Some non-genuine DS18B20 chips are fixed in 12-bit mode only, so the actual
86 The write-only sysfs entry ``eeprom_cmd`` is an alternative for EEPROM operations.
87 Write ``save`` to save device RAM to EEPROM. Write ``restore`` to restore EEPROM
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