Home
last modified time | relevance | path

Searched +full:write +full:- +full:protect (Results 1 – 25 of 92) sorted by relevance

1234

/Documentation/devicetree/bindings/nvmem/
Dnvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
23 "#address-cells":
26 "#size-cells":
29 read-only:
34 wp-gpios:
36 GPIO to which the write-protect pin of the chip is connected.
37 The write-protect GPIO is asserted, when it's driven high
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Darm,pl172.txt5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
/Documentation/admin-guide/mm/
Dpagemap.rst12 physical frame each virtual page is mapped to. It contains one 64-bit
16 * Bits 0-54 page frame number (PFN) if present
17 * Bits 0-4 swap type if swapped
18 * Bits 5-54 swap offset if swapped
19 * Bit 55 pte is soft-dirty (see
20 Documentation/admin-guide/mm/soft-dirty.rst)
22 * Bit 57 pte is uffd-wp write-protected (since 5.13) (see
23 Documentation/admin-guide/mm/userfaultfd.rst)
25 * Bits 59-60 zero
26 * Bit 61 page is file-page or shared-anon (since 3.5)
[all …]
Duserfaultfd.rst8 Userfaults allow the implementation of on-demand paging from userland
38 Vmas are not suitable for page- (or hugepage) granular fault tracking
48 is a corner case that would currently return ``-EBUSY``).
54 ----------------------
63 - Any user can always create a userfaultfd which traps userspace page faults
67 - In order to also trap kernel page faults for the address space, either the
84 --------------------------
101 - The ``UFFD_FEATURE_EVENT_*`` flags indicate that various other events
103 detail below in the `Non-cooperative userfaultfd`_ section.
105 - ``UFFD_FEATURE_MISSING_HUGETLBFS`` and ``UFFD_FEATURE_MISSING_SHMEM``
[all …]
/Documentation/devicetree/bindings/mmc/
Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
[all …]
Dmmc-spi-slot.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-spi-slot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml
14 - $ref: /schemas/spi/spi-peripheral-props.yaml
21 const: mmc-spi-slot
29 voltage-ranges:
30 $ref: /schemas/types.yaml#/definitions/uint32-matrix
[all …]
Dfsl,esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Frank Li <Frank.Li@nxp.com>
19 - enum:
20 - fsl,mpc8536-esdhc
21 - fsl,mpc8378-esdhc
22 - fsl,p2020-esdhc
23 - fsl,p4080-esdhc
24 - fsl,t1040-esdhc
[all …]
/Documentation/admin-guide/device-mapper/
Ddm-integrity.rst2 dm-integrity
5 The dm-integrity target emulates a block device that has additional
6 per-sector tags that can be used for storing integrity information.
9 writing the sector and the integrity tag must be atomic - i.e. in case of
12 To guarantee write atomicity, the dm-integrity target uses journal, it
16 The dm-integrity target can be used with the dm-crypt target - in this
17 situation the dm-crypt target creates the integrity data and passes them
18 to the dm-integrity target via bio_integrity_payload attached to the bio.
19 In this mode, the dm-crypt and dm-integrity targets provide authenticated
20 disk encryption - if the attacker modifies the encrypted device, an I/O
[all …]
/Documentation/devicetree/bindings/mtd/
Dlpc32xx-slc.txt4 - compatible: "nxp,lpc3220-slc"
5 - reg: Address and size of the controller
6 - nand-on-flash-bbt: Use bad block table on flash
7 - gpios: GPIO specification for NAND write protect
11 - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
12 - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
15 - nxp,wwidth: Write pulse width (W_WIDTH)
16 - nxp,whold: Write hold time (W_HOLD)
17 - nxp,wsetup: Write setup time (W_SETUP)
18 - nxp,rwidth: Read pulse width (R_WIDTH)
[all …]
Draw-nand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
21 The interpretation of these parameters is implementation-defined, so
28 pattern: "^nand@[a-f0-9]$"
32 Contains the chip-select IDs.
34 nand-ecc-placement:
[all …]
Dlpc32xx-mlc.txt4 - compatible: "nxp,lpc3220-mlc"
5 - reg: Address and size of the controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
13 - nxp,tcea_delay: TCEA_DELAY
14 - nxp,busy_delay: BUSY_DELAY
15 - nxp,nand_ta: NAND_TA
16 - nxp,rd_high: RD_HIGH
17 - nxp,rd_low: RD_LOW
18 - nxp,wr_high: WR_HIGH
[all …]
Dnvidia-tegra20-nand.txt4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
14 - reset-names: Must include the following entries:
[all …]
/Documentation/driver-api/md/
Draid5-ppl.rst10 array or using it is as degraded - data calculated from parity for array blocks
11 that have not been touched by a write request during the unclean shutdown can
12 be incorrect. Such condition is known as the RAID5 Write Hole. Because of
15 Partial parity for a write operation is the XOR of stripe data chunks not
16 modified by this write. It is just enough data needed for recovering from the
17 write hole. XORing partial parity with the modified chunks produces parity for
18 the stripe, consistent with its state before the write operation, regardless of
23 the array. Because of this, using write-intent bitmap and PPL together is not
26 When handling a write request PPL writes partial parity before new data and
27 parity are dispatched to disks. PPL is a distributed log - it is stored on
[all …]
/Documentation/accounting/
Ddelay-accounting.rst9 The per-task delay accounting functionality measures
18 g) write-protect copy
40 ---------
44 generic data structure to userspace corresponding to per-pid and per-tgid
53 cache, direct compact, write-protect copy, IRQ/SOFTIRQ etc.
60 When a task exits, records containing the per-task statistics
62 task of a thread group, the per-tgid statistics are also sent. More details
70 -----
96 getdelays [-dilv] [-t tgid] [-p pid]
100 # ./getdelays -d -p 10
[all …]
/Documentation/userspace-api/gpio/
Dsysfs.rst6 been moved to Documentation/ABI/obsolete/sysfs-gpio.
16 ----------------------
24 know for example that GPIO #23 controls the write protect line used to
25 protect boot loader segments in flash memory. System upgrade procedures
27 then changing its output state, then updating the code before re-enabling
28 the write protection. In normal use, GPIO #23 would never be touched,
38 Please read Documentation/driver-api/gpio/drivers-on-gpio.rst
44 --------------
47 - Control interfaces used to get userspace control over GPIOs;
49 - GPIOs themselves; and
[all …]
/Documentation/locking/
Dspinlocks.rst20 there is only one thread-of-control within the region(s) protected by that
26 Documentation/memory-barriers.txt
33 spinlock for most things - using more than one spinlock can make things a
40 before, because you have to make sure the spinlocks correctly protect the
45 NOTE! The spin-lock is safe only when you **also** use the lock itself
50 ----
52 Lesson 2: reader-writer spinlocks.
56 to mostly read from the shared variables, the reader-writer locks
59 to change the variables it has to get an exclusive write lock.
61 NOTE! reader-writer locks require more atomic memory operations than
[all …]
Dseqlock.rst8 Sequence counters are a reader-writer consistency mechanism with
9 lockless readers (read-only retry loops), and no writer starvation. They
24 the end of the write side critical section the sequence count becomes
27 A sequence counter write side critical section must never be preempted
30 interrupted writer. If that reader belongs to a real-time scheduling
42 This is the raw counting mechanism, which does not protect against
43 multiple writers. Write side critical sections must thus be serialized
46 If the write serialization primitive is not implicitly disabling
48 write side section. If the read section can be invoked from hardirq or
50 disabled before entering the write section.
[all …]
/Documentation/block/
Ddata-integrity.rst9 protect against data corruption. However, the detection of the
12 application tried to write is most likely lost.
38 As written, the protocol extensions only protect the path between
54 scatter-gather lists.
56 The controller will interleave the buffers on write and split them on
60 Also, the 16-bit CRC checksum mandated by both the SCSI and SATA specs
64 lighter-weight checksum to be used when interfacing with the operating
66 The IP checksum received from the OS is converted to the 16-bit CRC
90 they enable us to protect the entire path from application to storage
102 concept of an end-to-end protection scheme is a layering violation.
[all …]
/Documentation/devicetree/bindings/iio/potentiometer/
Drenesas,x9250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
18 - $ref: /schemas/spi/spi-peripheral-props.yaml
23 - renesas,x9250t
24 - renesas,x9250u
29 vcc-supply:
33 avp-supply:
37 avn-supply:
[all …]
/Documentation/core-api/
Dmemory-hotplug.rst63 - start_pfn is start_pfn of online/offline memory.
64 - nr_pages is # of pages of online/offline memory.
65 - status_change_nid_normal is set node id when N_NORMAL_MEMORY of nodemask
66 is (will be) set/clear, if this is -1, then nodemask status is not changed.
67 - status_change_nid is set node id when N_MEMORY of nodemask is (will be)
69 node loses all memory. If this is -1, then nodemask status is not changed.
92 - synchronize against online/offline requests (e.g. via sysfs). This way, memory
96 - synchronize against CPU hotplug and similar (e.g. relevant for ACPI and PPC)
102 - device_online() will first take the device_lock(), followed by
104 - add_memory_resource() will first take the mem_hotplug_lock, followed by
[all …]
/Documentation/arch/x86/
Dmtrr.rst1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Richard Gooch <rgooch@atnf.csiro.au> - 3 Jun 1999
8 - Luis R. Rodriguez <mcgrof@do-not-panic.com> - April 9, 2015
17 non-PAT systems while a no-op but equally effective on PAT enabled systems.
37 a video (VGA) card on a PCI or AGP bus. Enabling write-combining
38 allows bus write transfers to be combined into a larger transfer
40 of image write operations 2.5 times or more.
46 The AMD K6-2 (stepping 8 and above) and K6-3 processors have two
50 The Centaur C6 (WinChip) has 8 MCRs, allowing write-combining. These
62 which allows you to read and write. The other is an ioctl()
[all …]
/Documentation/driver-api/mmc/
Dmmc-dev-attrs.rst8 The following attributes are read/write.
11 force_ro Enforce read-only access even if write protect switch is off.
17 All attributes are read-only.
37 rel_sectors Reliable write sector count
52 if the card is block-addressed, 0 otherwise.
62 duration of the erase - which could be a several
76 For MMC, "preferred_erase_size" is the high-capacity
/Documentation/driver-api/mtd/
Dspi-intel.rst2 Upgrading BIOS using spi-intel
11 Not all manufacturers protect the SPI serial flash, mainly because it
14 The spi-intel driver makes it possible to read and write the SPI serial
16 any of them set, the whole MTD device is made read-only to prevent
18 contents as read-only but it can be changed from kernel command line,
31 2) Install mtd-utils package [2]. We need this in order to erase the SPI
33 name "mtd-utils".
67 Erasing 4 Kibyte @ 7ff000 -- 100 % complete
69 8) Once completed without errors you can write the new BIOS image::
86 ----------
[all …]
/Documentation/mm/
Dmmu_notifier.rst14 B) a page table entry is updated to point to a new page (COW, write fault
17 Case A is obvious you do not want to take the risk for the device to write to
23 - take page table lock
24 - clear page table entry and notify ([pmd/pte]p_huge_clear_flush_notify())
25 - set page table entry to point to new page
33 Two address addrA and addrB such that \|addrA - addrB\| >= PAGE_SIZE we assume
34 they are write protected for COW (other case of B apply too).
38 [Time N] --------------------------------------------------------------------
39 CPU-thread-0 {try to write to addrA}
40 CPU-thread-1 {try to write to addrB}
[all …]
/Documentation/power/
Dswsusp.rst47 - If you feel ACPI works pretty well on your system, you might try::
51 - If you would like to write hibernation image to swap and then suspend
56 - If you have SATA disks, you'll need recent kernels with SATA suspend
58 are built into kernel -- not modules. [There's way to make
68 - The resume process checks for the presence of the resume device,
72 - The resume process may be triggered in two ways:
81 read-only) otherwise data may be corrupted.
87 Last revised: 2003-10-20 by Pavel Machek
90 -------------------------
109 of the hardware, write to the filesystems, etc.
[all …]

1234