Searched full:xilinx (Results 1 – 25 of 81) sorted by relevance
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| /Documentation/devicetree/bindings/ |
| D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
4 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
89 That covers the general approach to binding xilinx IP cores into the
92 i) Xilinx ML300 Framebuffer
105 ii) Xilinx SystemACE
107 The Xilinx SystemACE device is used to program FPGAs from an FPGA
114 iii) Xilinx EMAC and Xilinx TEMAC
116 Xilinx Ethernet devices. In addition to general xilinx properties
121 iv) Xilinx Uartlite
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| /Documentation/devicetree/bindings/soc/xilinx/ |
| D | xilinx.yaml | 4 $id: http://devicetree.org/schemas/soc/xilinx/xilinx.yaml#
7 title: Xilinx Zynq Platforms
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
52 - description: Xilinx internal board zc1232
58 - description: Xilinx internal board zc1254
64 - description: Xilinx evaluation board zcu1275
70 - description: Xilinx 96boards compatible board zcu100
76 - description: Xilinx 96boards compatible board Ultra96
84 - description: Xilinx evaluation board zcu102
94 - description: Xilinx evaluation board zcu104
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| D | xlnx,vcu-settings.yaml | 4 $id: http://devicetree.org/schemas/soc/xilinx/xlnx,vcu-settings.yaml#
7 title: Xilinx VCU Settings
13 The Xilinx VCU Settings provides information about the configuration of the
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| /Documentation/ABI/stable/ |
| D | sysfs-driver-firmware-zynqmp | 4 Contact: "Jolly Shah" <jollys@xilinx.com>
13 other Xilinx software products: GLOBAL_GEN_STORAGE{4:6}.
25 Users: Xilinx
30 Contact: "Jolly Shah" <jollys@xilinx.com>
40 Four registers are used by the FSBL and other Xilinx
54 Users: Xilinx
59 Contact: "Jolly Shah" <jollys@xilinx.com>
91 Users: Xilinx
96 Contact: "Jolly Shah" <jollys@xilinx.com>
115 Users: Xilinx
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | xilinx-xadc.txt | 1 Xilinx XADC device driver
3 This binding document describes the bindings for the Xilinx 7 Series XADC as well
6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
14 The Xilinx System Monitor is an ADC that is found in the UltraScale and
15 UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
16 communication. Xilinx provides a standard IP core that can be used to access the
18 called the Xilinx System Management Wizard. This document describes the bindings
28 Xilinx System Management Wizard fabric IP core to access the
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| /Documentation/devicetree/bindings/fpga/ |
| D | xlnx,fpga-slave-serial.yaml | 7 title: Xilinx Slave Serial SPI FPGA
13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
19 https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
20 https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
21 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
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| D | xlnx,pr-decoupler.yaml | 7 title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
16 The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
21 Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager Softcore
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
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| D | xlnx,fpga-selectmap.yaml | 7 title: Xilinx SelectMAP FPGA interface
13 Xilinx 7 Series FPGAs support a method of loading the bitstream over a
19 https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
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| D | xilinx-zynq-fpga-mgr.yaml | 4 $id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
7 title: Xilinx Zynq FPGA Manager
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
18 The following properties are common to all Xilinx video IP cores.
35 [UG934] https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_vi…
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| D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
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| D | xlnx,csi2rxss.yaml | 4 $id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
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| /Documentation/admin-guide/media/ |
| D | platform-cardlist.rst | 76 xilinx-tpg Xilinx Video Test Pattern Generator
77 xilinx-video Xilinx Video IP (EXPERIMENTAL)
78 xilinx-vtc Xilinx Video Timing Controller
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| /Documentation/devicetree/bindings/dma/xilinx/ |
| D | xlnx,zynqmp-dpdma.yaml | 4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
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| D | xlnx,zynqmp-dma-1.0.yaml | 4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
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| D | xilinx_dma.txt | 1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
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| /Documentation/driver-api/xilinx/ |
| D | eemi.rst | 2 Xilinx Zynq MPSoC EEMI Documentation
5 Xilinx Zynq MPSoC Firmware Interface
40 https://www.xilinx.com/support/documentation/user_guides/ug1200-eemi-api.pdf
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| D | index.rst | 3 Xilinx FPGA
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| /Documentation/devicetree/bindings/mailbox/ |
| D | xlnx,zynqmp-ipi-mailbox.yaml | 7 title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
10 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
11 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
15 | Xilinx ZynqMP IPI Controller |
32 | Xilinx IPI Agent Block |
71 Remote Xilinx IPI agent ID of which the mailbox is connected to.
101 Remote Xilinx IPI agent ID of which the mailbox is connected to.
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| /Documentation/devicetree/bindings/spi/ |
| D | xlnx,zynq-qspi.yaml | 7 title: Xilinx Zynq QSPI controller
10 The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
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| D | spi-xilinx.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-xilinx.yaml#
7 title: Xilinx SPI controller
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| /Documentation/devicetree/bindings/net/ |
| D | cdns,macb.yaml | 23 - cdns,zynq-gem # Xilinx Zynq-7xxx SoC
24 - cdns,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
30 - xlnx,versal-gem # Xilinx Versal
31 - xlnx,zynq-gem # Xilinx Zynq-7xxx SoC
32 - xlnx,zynqmp-gem # Xilinx Zynq Ultrascale+ MPSoC
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| /Documentation/devicetree/bindings/clock/ |
| D | xlnx,clocking-wizard.yaml | 7 title: Xilinx clocking wizard
13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
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| /Documentation/devicetree/bindings/rtc/ |
| D | xlnx,zynqmp-rtc.yaml | 7 title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
10 RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
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| /Documentation/devicetree/bindings/net/can/ |
| D | xilinx,can.yaml | 4 $id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
8 Xilinx CAN and CANFD controller
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
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