Searched +full:xusb +full:- +full:padctl (Results 1 – 11 of 11) sorted by relevance
| /Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra124-xusb-padctl.txt | 1 Device tree binding for NVIDIA Tegra XUSB pad controller 4 NOTE: It turns out that this binding isn't an accurate description of the XUSB 7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt. 10 The Tegra XUSB pad controller manages a set of lanes, each of which can be 14 This document defines the device-specific binding for the XUSB pad controller. 16 Refer to pinctrl-bindings.txt in this directory for generic information about 17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on 21 -------------------- 22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl". 23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl", [all …]
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| /Documentation/devicetree/bindings/usb/ |
| D | nvidia,tegra124-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 exposed by the Tegra XUSB pad controller. 20 - description: NVIDIA Tegra124 21 const: nvidia,tegra124-xusb 23 - description: NVIDIA Tegra132 [all …]
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| D | nvidia,tegra-xudc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra XUSB device mode controller (XUDC) 14 - Nagarjuna Kristam <nkristam@nvidia.com> 15 - JC Kuo <jckuo@nvidia.com> 16 - Thierry Reding <treding@nvidia.com> 21 - enum: 22 - nvidia,tegra210-xudc # For Tegra210 [all …]
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| D | nvidia,tegra186-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 exposed by the Tegra XUSB pad controller. 18 const: nvidia,tegra186-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers [all …]
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| D | nvidia,tegra210-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 exposed by the Tegra XUSB pad controller. 18 const: nvidia,tegra210-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers [all …]
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| D | nvidia,tegra234-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 the Tegra XUSB pad controller. The xHCI controller controls up to eight 20 const: nvidia,tegra234-xusb 24 - description: xHCI host registers 25 - description: XUSB FPCI registers [all …]
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| D | nvidia,tegra194-xusb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 exposed by the Tegra XUSB pad controller. 18 const: nvidia,tegra194-xusb 22 - description: base and length of the xHCI host registers 23 - description: base and length of the XUSB FPCI registers [all …]
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| /Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra186 XUSB pad controller 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
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| D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra194 XUSB pad controller 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
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| D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra124 XUSB pad controller 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
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| D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra210 XUSB pad controller 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed [all …]
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