Searched +full:zynqmp +full:- +full:pcap +full:- +full:fpga (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager10 - Nava kishore Manne <nava.kishore.manne@amd.com>13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.14 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to20 const: xlnx,zynqmp-pcap-fpga23 - compatible[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Nava kishore Manne <nava.kishore.manne@amd.com>12 description: The zynqmp-firmware node describes the interface to platform13 firmware. ZynqMP has an interface to communicate with secure firmware.17 power management service, FPGA service and other platform management23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.24 const: xlnx,zynqmp-firmware[all …]
1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status5 Description: (RO) Read fpga status.7 of the FPGA device. Each bit position in the status value is9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration24 BIT(4) 0: Start-up sequence has not finished25 1: Start-up sequence has finished27 BIT(5) 0: All I/Os are placed in High-Z state30 BIT(6) 0: Flip-flops and block RAM are write disabled31 1: Flip-flops and block RAM are write enabled54 BIT(17) System Monitor over-temperature if set[all …]