1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Condor board with R-Car V3H 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 aliases { 12 i2c0 = &i2c0; 13 i2c1 = &i2c1; 14 i2c2 = &i2c2; 15 i2c3 = &i2c3; 16 i2c4 = &i2c4; 17 i2c5 = &i2c5; 18 serial0 = &scif0; 19 ethernet0 = &gether; 20 }; 21 22 chosen { 23 stdout-path = "serial0:115200n8"; 24 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 25 }; 26 27 d1_8v: regulator-2 { 28 compatible = "regulator-fixed"; 29 regulator-name = "D1.8V"; 30 regulator-min-microvolt = <1800000>; 31 regulator-max-microvolt = <1800000>; 32 regulator-boot-on; 33 regulator-always-on; 34 }; 35 36 d3_3v: regulator-0 { 37 compatible = "regulator-fixed"; 38 regulator-name = "D3.3V"; 39 regulator-min-microvolt = <3300000>; 40 regulator-max-microvolt = <3300000>; 41 regulator-boot-on; 42 regulator-always-on; 43 }; 44 45 hdmi-out { 46 compatible = "hdmi-connector"; 47 type = "a"; 48 49 port { 50 hdmi_con: endpoint { 51 remote-endpoint = <&adv7511_out>; 52 }; 53 }; 54 }; 55 56 lvds-decoder { 57 compatible = "thine,thc63lvd1024"; 58 vcc-supply = <&d3_3v>; 59 60 ports { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 64 port@0 { 65 reg = <0>; 66 thc63lvd1024_in: endpoint { 67 remote-endpoint = <&lvds0_out>; 68 }; 69 }; 70 71 port@2 { 72 reg = <2>; 73 thc63lvd1024_out: endpoint { 74 remote-endpoint = <&adv7511_in>; 75 }; 76 }; 77 }; 78 }; 79 80 memory@48000000 { 81 device_type = "memory"; 82 /* first 128MB is reserved for secure area. */ 83 reg = <0 0x48000000 0 0x78000000>; 84 }; 85 86 vddq_vin01: regulator-1 { 87 compatible = "regulator-fixed"; 88 regulator-name = "VDDQ_VIN01"; 89 regulator-min-microvolt = <1800000>; 90 regulator-max-microvolt = <1800000>; 91 regulator-boot-on; 92 regulator-always-on; 93 }; 94 95 x1_clk: x1-clock { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <148500000>; 99 }; 100}; 101 102&canfd { 103 pinctrl-0 = <&canfd0_pins>; 104 pinctrl-names = "default"; 105 status = "okay"; 106 107 channel0 { 108 status = "okay"; 109 }; 110}; 111 112&csi40 { 113 status = "okay"; 114 115 ports { 116 port@0 { 117 csi40_in: endpoint { 118 clock-lanes = <0>; 119 data-lanes = <1 2 3 4>; 120 remote-endpoint = <&max9286_out0>; 121 }; 122 }; 123 }; 124}; 125 126&csi41 { 127 status = "okay"; 128 129 ports { 130 port@0 { 131 csi41_in: endpoint { 132 clock-lanes = <0>; 133 data-lanes = <1 2 3 4>; 134 remote-endpoint = <&max9286_out1>; 135 }; 136 }; 137 }; 138}; 139 140&du { 141 clocks = <&cpg CPG_MOD 724>, 142 <&x1_clk>; 143 clock-names = "du.0", "dclkin.0"; 144 status = "okay"; 145}; 146 147&extal_clk { 148 clock-frequency = <16666666>; 149}; 150 151&extalr_clk { 152 clock-frequency = <32768>; 153}; 154 155&gether { 156 pinctrl-0 = <&gether_pins>; 157 pinctrl-names = "default"; 158 159 phy-mode = "rgmii-id"; 160 phy-handle = <&phy0>; 161 renesas,no-ether-link; 162 status = "okay"; 163 164 phy0: ethernet-phy@0 { 165 compatible = "ethernet-phy-id0022.1622", 166 "ethernet-phy-ieee802.3-c22"; 167 rxc-skew-ps = <1500>; 168 reg = <0>; 169 interrupts-extended = <&gpio4 23 IRQ_TYPE_LEVEL_LOW>; 170 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 171 }; 172}; 173 174&i2c0 { 175 pinctrl-0 = <&i2c0_pins>; 176 pinctrl-names = "default"; 177 178 status = "okay"; 179 clock-frequency = <400000>; 180 181 io_expander0: gpio@20 { 182 compatible = "onnn,pca9654"; 183 reg = <0x20>; 184 gpio-controller; 185 #gpio-cells = <2>; 186 }; 187 188 io_expander1: gpio@21 { 189 compatible = "onnn,pca9654"; 190 reg = <0x21>; 191 gpio-controller; 192 #gpio-cells = <2>; 193 }; 194 195 hdmi@39 { 196 compatible = "adi,adv7511w"; 197 reg = <0x39>; 198 interrupt-parent = <&gpio1>; 199 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 200 avdd-supply = <&d1_8v>; 201 dvdd-supply = <&d1_8v>; 202 pvdd-supply = <&d1_8v>; 203 bgvdd-supply = <&d1_8v>; 204 dvdd-3v-supply = <&d3_3v>; 205 206 adi,input-depth = <8>; 207 adi,input-colorspace = "rgb"; 208 adi,input-clock = "1x"; 209 210 ports { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 214 port@0 { 215 reg = <0>; 216 adv7511_in: endpoint { 217 remote-endpoint = <&thc63lvd1024_out>; 218 }; 219 }; 220 221 port@1 { 222 reg = <1>; 223 adv7511_out: endpoint { 224 remote-endpoint = <&hdmi_con>; 225 }; 226 }; 227 }; 228 }; 229 230 eeprom@50 { 231 compatible = "rohm,br24t01", "atmel,24c01"; 232 reg = <0x50>; 233 pagesize = <8>; 234 }; 235}; 236 237&i2c1 { 238 pinctrl-0 = <&i2c1_pins>; 239 pinctrl-names = "default"; 240 241 status = "okay"; 242 clock-frequency = <400000>; 243 244 gmsl0: gmsl-deserializer@48 { 245 compatible = "maxim,max9286"; 246 reg = <0x48>; 247 248 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; 249 enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>; 250 251 ports { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 255 port@0 { 256 reg = <0>; 257 }; 258 259 port@1 { 260 reg = <1>; 261 }; 262 263 port@2 { 264 reg = <2>; 265 }; 266 267 port@3 { 268 reg = <3>; 269 }; 270 271 port@4 { 272 reg = <4>; 273 max9286_out0: endpoint { 274 clock-lanes = <0>; 275 data-lanes = <1 2 3 4>; 276 remote-endpoint = <&csi40_in>; 277 }; 278 }; 279 }; 280 281 i2c-mux { 282 #address-cells = <1>; 283 #size-cells = <0>; 284 285 i2c@0 { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 reg = <0>; 289 290 status = "disabled"; 291 }; 292 293 i2c@1 { 294 #address-cells = <1>; 295 #size-cells = <0>; 296 reg = <1>; 297 298 status = "disabled"; 299 }; 300 301 i2c@2 { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 reg = <2>; 305 306 status = "disabled"; 307 }; 308 309 i2c@3 { 310 #address-cells = <1>; 311 #size-cells = <0>; 312 reg = <3>; 313 314 status = "disabled"; 315 }; 316 }; 317 }; 318 319 gmsl1: gmsl-deserializer@4a { 320 compatible = "maxim,max9286"; 321 reg = <0x4a>; 322 323 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; 324 enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>; 325 326 ports { 327 #address-cells = <1>; 328 #size-cells = <0>; 329 330 port@0 { 331 reg = <0>; 332 }; 333 334 port@1 { 335 reg = <1>; 336 }; 337 338 port@2 { 339 reg = <2>; 340 }; 341 342 port@3 { 343 reg = <3>; 344 }; 345 346 port@4 { 347 reg = <4>; 348 max9286_out1: endpoint { 349 clock-lanes = <0>; 350 data-lanes = <1 2 3 4>; 351 remote-endpoint = <&csi41_in>; 352 }; 353 }; 354 }; 355 356 i2c-mux { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 360 i2c@0 { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 reg = <0>; 364 365 status = "disabled"; 366 }; 367 368 i2c@1 { 369 #address-cells = <1>; 370 #size-cells = <0>; 371 reg = <1>; 372 373 status = "disabled"; 374 }; 375 376 i2c@2 { 377 #address-cells = <1>; 378 #size-cells = <0>; 379 reg = <2>; 380 381 status = "disabled"; 382 }; 383 384 i2c@3 { 385 #address-cells = <1>; 386 #size-cells = <0>; 387 reg = <3>; 388 389 status = "disabled"; 390 }; 391 }; 392 }; 393}; 394 395&lvds0 { 396 status = "okay"; 397 398 ports { 399 port@1 { 400 lvds0_out: endpoint { 401 remote-endpoint = <&thc63lvd1024_in>; 402 }; 403 }; 404 }; 405}; 406 407&mmc0 { 408 pinctrl-0 = <&mmc_pins>; 409 pinctrl-1 = <&mmc_pins>; 410 pinctrl-names = "default", "state_uhs"; 411 412 vmmc-supply = <&d3_3v>; 413 vqmmc-supply = <&vddq_vin01>; 414 mmc-hs200-1_8v; 415 bus-width = <8>; 416 no-sd; 417 no-sdio; 418 non-removable; 419 status = "okay"; 420}; 421 422&pciec { 423 status = "okay"; 424}; 425 426&pcie_bus_clk { 427 clock-frequency = <100000000>; 428}; 429 430&pcie_phy { 431 status = "okay"; 432}; 433 434&pfc { 435 canfd0_pins: canfd0 { 436 groups = "canfd0_data_a"; 437 function = "canfd0"; 438 }; 439 440 gether_pins: gether { 441 groups = "gether_mdio_a", "gether_rgmii", 442 "gether_txcrefclk", "gether_txcrefclk_mega"; 443 function = "gether"; 444 }; 445 446 i2c0_pins: i2c0 { 447 groups = "i2c0"; 448 function = "i2c0"; 449 }; 450 451 i2c1_pins: i2c1 { 452 groups = "i2c1"; 453 function = "i2c1"; 454 }; 455 456 mmc_pins: mmc { 457 groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; 458 function = "mmc"; 459 power-source = <1800>; 460 }; 461 462 qspi0_pins: qspi0 { 463 groups = "qspi0_ctrl", "qspi0_data4"; 464 function = "qspi0"; 465 }; 466 467 scif0_pins: scif0 { 468 groups = "scif0_data"; 469 function = "scif0"; 470 }; 471 472 scif_clk_pins: scif_clk { 473 groups = "scif_clk_b"; 474 function = "scif_clk"; 475 }; 476}; 477 478&rpc { 479 pinctrl-0 = <&qspi0_pins>; 480 pinctrl-names = "default"; 481 482 status = "okay"; 483 484 flash@0 { 485 compatible = "spansion,s25fs512s", "jedec,spi-nor"; 486 reg = <0>; 487 spi-max-frequency = <50000000>; 488 spi-rx-bus-width = <4>; 489 490 partitions { 491 compatible = "fixed-partitions"; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 495 bootparam@0 { 496 reg = <0x00000000 0x040000>; 497 read-only; 498 }; 499 cr7@40000 { 500 reg = <0x00040000 0x080000>; 501 read-only; 502 }; 503 cert_header_sa3@c0000 { 504 reg = <0x000c0000 0x080000>; 505 read-only; 506 }; 507 bl2@140000 { 508 reg = <0x00140000 0x040000>; 509 read-only; 510 }; 511 cert_header_sa6@180000 { 512 reg = <0x00180000 0x040000>; 513 read-only; 514 }; 515 bl31@1c0000 { 516 reg = <0x001c0000 0x460000>; 517 read-only; 518 }; 519 uboot@640000 { 520 reg = <0x00640000 0x0c0000>; 521 read-only; 522 }; 523 uboot-env@700000 { 524 reg = <0x00700000 0x040000>; 525 read-only; 526 }; 527 dtb@740000 { 528 reg = <0x00740000 0x080000>; 529 }; 530 kernel@7c0000 { 531 reg = <0x007c0000 0x1400000>; 532 }; 533 user@1bc0000 { 534 reg = <0x01bc0000 0x2440000>; 535 }; 536 }; 537 }; 538}; 539 540&rwdt { 541 timeout-sec = <60>; 542 status = "okay"; 543}; 544 545&scif0 { 546 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; 547 pinctrl-names = "default"; 548 549 status = "okay"; 550}; 551 552&scif_clk { 553 clock-frequency = <14745600>; 554}; 555