1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _CORESIGHT_PRIV_H
7 #define _CORESIGHT_PRIV_H
8
9 #include <linux/amba/bus.h>
10 #include <linux/bitops.h>
11 #include <linux/io.h>
12 #include <linux/coresight.h>
13 #include <linux/pm_runtime.h>
14
15 extern struct mutex coresight_mutex;
16 extern const struct device_type coresight_dev_type[];
17
18 /*
19 * Coresight management registers (0xf00-0xfcc)
20 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
21 * Trace registers in PFTv1.1
22 */
23 #define CORESIGHT_ITCTRL 0xf00
24 #define CORESIGHT_CLAIMSET 0xfa0
25 #define CORESIGHT_CLAIMCLR 0xfa4
26 #define CORESIGHT_LAR 0xfb0
27 #define CORESIGHT_LSR 0xfb4
28 #define CORESIGHT_DEVARCH 0xfbc
29 #define CORESIGHT_AUTHSTATUS 0xfb8
30 #define CORESIGHT_DEVID 0xfc8
31 #define CORESIGHT_DEVTYPE 0xfcc
32
33
34 /*
35 * Coresight device CLAIM protocol.
36 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
37 */
38 #define CORESIGHT_CLAIM_MASK GENMASK(1, 0)
39 #define CORESIGHT_CLAIM_SELF_HOSTED BIT(1)
40
41 #define TIMEOUT_US 100
42 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
43
44 #define ETM_MODE_EXCL_KERN BIT(30)
45 #define ETM_MODE_EXCL_USER BIT(31)
46 struct cs_pair_attribute {
47 struct device_attribute attr;
48 u32 lo_off;
49 u32 hi_off;
50 };
51
52 struct cs_off_attribute {
53 struct device_attribute attr;
54 u32 off;
55 };
56
57 extern ssize_t coresight_simple_show32(struct device *_dev,
58 struct device_attribute *attr, char *buf);
59 extern ssize_t coresight_simple_show_pair(struct device *_dev,
60 struct device_attribute *attr, char *buf);
61
62 #define coresight_simple_reg32(name, offset) \
63 (&((struct cs_off_attribute[]) { \
64 { \
65 __ATTR(name, 0444, coresight_simple_show32, NULL), \
66 offset \
67 } \
68 })[0].attr.attr)
69
70 #define coresight_simple_reg64(name, lo_off, hi_off) \
71 (&((struct cs_pair_attribute[]) { \
72 { \
73 __ATTR(name, 0444, coresight_simple_show_pair, NULL), \
74 lo_off, hi_off \
75 } \
76 })[0].attr.attr)
77
78 extern const u32 coresight_barrier_pkt[4];
79 #define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt))
80
81 enum etm_addr_type {
82 ETM_ADDR_TYPE_NONE,
83 ETM_ADDR_TYPE_SINGLE,
84 ETM_ADDR_TYPE_RANGE,
85 ETM_ADDR_TYPE_START,
86 ETM_ADDR_TYPE_STOP,
87 };
88
89 /**
90 * struct cs_buffer - keep track of a recording session' specifics
91 * @cur: index of the current buffer
92 * @nr_pages: max number of pages granted to us
93 * @pid: PID this cs_buffer belongs to
94 * @offset: offset within the current buffer
95 * @data_size: how much we collected in this run
96 * @snapshot: is this run in snapshot mode
97 * @data_pages: a handle the ring buffer
98 */
99 struct cs_buffers {
100 unsigned int cur;
101 unsigned int nr_pages;
102 pid_t pid;
103 unsigned long offset;
104 local_t data_size;
105 bool snapshot;
106 void **data_pages;
107 };
108
coresight_insert_barrier_packet(void * buf)109 static inline void coresight_insert_barrier_packet(void *buf)
110 {
111 if (buf)
112 memcpy(buf, coresight_barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
113 }
114
CS_LOCK(void __iomem * addr)115 static inline void CS_LOCK(void __iomem *addr)
116 {
117 do {
118 /* Wait for things to settle */
119 mb();
120 writel_relaxed(0x0, addr + CORESIGHT_LAR);
121 } while (0);
122 }
123
CS_UNLOCK(void __iomem * addr)124 static inline void CS_UNLOCK(void __iomem *addr)
125 {
126 do {
127 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
128 /* Make sure everyone has seen this */
129 mb();
130 } while (0);
131 }
132
133 void coresight_disable_path(struct list_head *path);
134 int coresight_enable_path(struct list_head *path, enum cs_mode mode,
135 void *sink_data);
136 struct coresight_device *coresight_get_sink(struct list_head *path);
137 struct coresight_device *coresight_get_sink_by_id(u32 id);
138 struct coresight_device *
139 coresight_find_default_sink(struct coresight_device *csdev);
140 struct list_head *coresight_build_path(struct coresight_device *csdev,
141 struct coresight_device *sink);
142 void coresight_release_path(struct list_head *path);
143 int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
144 void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
145 int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
146 void coresight_remove_conns_sysfs_group(struct coresight_device *csdev);
147 int coresight_make_links(struct coresight_device *orig,
148 struct coresight_connection *conn,
149 struct coresight_device *target);
150 void coresight_remove_links(struct coresight_device *orig,
151 struct coresight_connection *conn);
152 u32 coresight_get_sink_id(struct coresight_device *csdev);
153
154 #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
155 extern int etm_readl_cp14(u32 off, unsigned int *val);
156 extern int etm_writel_cp14(u32 off, u32 val);
157 #else
etm_readl_cp14(u32 off,unsigned int * val)158 static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
etm_writel_cp14(u32 off,u32 val)159 static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
160 #endif
161
162 struct cti_assoc_op {
163 void (*add)(struct coresight_device *csdev);
164 void (*remove)(struct coresight_device *csdev);
165 };
166
167 extern void coresight_set_cti_ops(const struct cti_assoc_op *cti_op);
168 extern void coresight_remove_cti_ops(void);
169
170 /*
171 * Macros and inline functions to handle CoreSight UCI data and driver
172 * private data in AMBA ID table entries, and extract data values.
173 */
174
175 /* coresight AMBA ID, no UCI, no driver data: id table entry */
176 #define CS_AMBA_ID(pid) \
177 { \
178 .id = pid, \
179 .mask = 0x000fffff, \
180 }
181
182 /* coresight AMBA ID, UCI with driver data only: id table entry. */
183 #define CS_AMBA_ID_DATA(pid, dval) \
184 { \
185 .id = pid, \
186 .mask = 0x000fffff, \
187 .data = (void *)&(struct amba_cs_uci_id) \
188 { \
189 .data = (void *)dval, \
190 } \
191 }
192
193 /* coresight AMBA ID, full UCI structure: id table entry. */
194 #define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \
195 { \
196 .id = pid, \
197 .mask = m, \
198 .data = (void *)uci_ptr \
199 }
200 #define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci)
201 /*
202 * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the
203 * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that
204 * as a match value for blanket matching all devices in the given CoreSight
205 * device type and architecture.
206 */
207 #define PIDR2_JEDEC BIT(3)
208 #define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16)
209 /*
210 * Match all PIDs in a given CoreSight device type and architecture, defined
211 * by the uci.
212 */
213 #define CS_AMBA_MATCH_ALL_UCI(uci) \
214 __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
215
216 /* extract the data value from a UCI structure given amba_id pointer. */
coresight_get_uci_data(const struct amba_id * id)217 static inline void *coresight_get_uci_data(const struct amba_id *id)
218 {
219 struct amba_cs_uci_id *uci_id = id->data;
220
221 if (!uci_id)
222 return NULL;
223
224 return uci_id->data;
225 }
226
coresight_get_uci_data_from_amba(const struct amba_id * table,u32 pid)227 static inline void *coresight_get_uci_data_from_amba(const struct amba_id *table, u32 pid)
228 {
229 while (table->mask) {
230 if ((pid & table->mask) == table->id)
231 return coresight_get_uci_data(table);
232 table++;
233 };
234 return NULL;
235 }
236
237 void coresight_release_platform_data(struct coresight_device *csdev,
238 struct device *dev,
239 struct coresight_platform_data *pdata);
240 struct coresight_device *
241 coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode);
242 void coresight_add_helper(struct coresight_device *csdev,
243 struct coresight_device *helper);
244
245 void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev);
246 struct coresight_device *coresight_get_percpu_sink(int cpu);
247 void coresight_disable_source(struct coresight_device *csdev, void *data);
248
249 #endif
250