1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "timing_generator.h"
29 #include "hw_sequencer.h"
30 #include "hw_sequencer_private.h"
31 #include "basics/dc_common.h"
32 #include "resource.h"
33 #include "dc_dmub_srv.h"
34 #include "dc_state_priv.h"
35
36 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
37
38 /* used as index in array of black_color_format */
39 enum black_color_format {
40 BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0,
41 BLACK_COLOR_FORMAT_RGB_LIMITED,
42 BLACK_COLOR_FORMAT_YUV_TV,
43 BLACK_COLOR_FORMAT_YUV_CV,
44 BLACK_COLOR_FORMAT_YUV_SUPER_AA,
45 BLACK_COLOR_FORMAT_DEBUG,
46 };
47
48 enum dc_color_space_type {
49 COLOR_SPACE_RGB_TYPE,
50 COLOR_SPACE_RGB_LIMITED_TYPE,
51 COLOR_SPACE_YCBCR601_TYPE,
52 COLOR_SPACE_YCBCR709_TYPE,
53 COLOR_SPACE_YCBCR2020_TYPE,
54 COLOR_SPACE_YCBCR601_LIMITED_TYPE,
55 COLOR_SPACE_YCBCR709_LIMITED_TYPE,
56 COLOR_SPACE_YCBCR709_BLACK_TYPE,
57 };
58
59 static const struct tg_color black_color_format[] = {
60 /* BlackColorFormat_RGB_FullRange */
61 {0, 0, 0},
62 /* BlackColorFormat_RGB_Limited */
63 {0x40, 0x40, 0x40},
64 /* BlackColorFormat_YUV_TV */
65 {0x200, 0x40, 0x200},
66 /* BlackColorFormat_YUV_CV */
67 {0x1f4, 0x40, 0x1f4},
68 /* BlackColorFormat_YUV_SuperAA */
69 {0x1a2, 0x20, 0x1a2},
70 /* visual confirm debug */
71 {0xff, 0xff, 0},
72 };
73
74 struct out_csc_color_matrix_type {
75 enum dc_color_space_type color_space_type;
76 uint16_t regval[12];
77 };
78
79 static const struct out_csc_color_matrix_type output_csc_matrix[] = {
80 { COLOR_SPACE_RGB_TYPE,
81 { 0x2000, 0, 0, 0,
82 0, 0x2000, 0, 0,
83 0, 0, 0x2000, 0} },
84 { COLOR_SPACE_RGB_LIMITED_TYPE,
85 { 0x1B67, 0, 0, 0x201,
86 0, 0x1B67, 0, 0x201,
87 0, 0, 0x1B67, 0x201} },
88 { COLOR_SPACE_YCBCR601_TYPE,
89 { 0xE04, 0xF444, 0xFDB9, 0x1004,
90 0x831, 0x1016, 0x320, 0x201,
91 0xFB45, 0xF6B7, 0xE04, 0x1004} },
92 { COLOR_SPACE_YCBCR709_TYPE,
93 { 0xE04, 0xF345, 0xFEB7, 0x1004,
94 0x5D3, 0x1399, 0x1FA, 0x201,
95 0xFCCA, 0xF533, 0xE04, 0x1004} },
96 /* TODO: correct values below */
97 { COLOR_SPACE_YCBCR601_LIMITED_TYPE,
98 { 0xE00, 0xF447, 0xFDB9, 0x1000,
99 0x991, 0x12C9, 0x3A6, 0x200,
100 0xFB47, 0xF6B9, 0xE00, 0x1000} },
101 { COLOR_SPACE_YCBCR709_LIMITED_TYPE,
102 { 0xE00, 0xF349, 0xFEB7, 0x1000,
103 0x6CE, 0x16E3, 0x24F, 0x200,
104 0xFCCB, 0xF535, 0xE00, 0x1000} },
105 { COLOR_SPACE_YCBCR2020_TYPE,
106 { 0x1000, 0xF149, 0xFEB7, 0x1004,
107 0x0868, 0x15B2, 0x01E6, 0x201,
108 0xFB88, 0xF478, 0x1000, 0x1004} },
109 { COLOR_SPACE_YCBCR709_BLACK_TYPE,
110 { 0x0000, 0x0000, 0x0000, 0x1000,
111 0x0000, 0x0000, 0x0000, 0x0200,
112 0x0000, 0x0000, 0x0000, 0x1000} },
113 };
114
is_rgb_type(enum dc_color_space color_space)115 static bool is_rgb_type(
116 enum dc_color_space color_space)
117 {
118 bool ret = false;
119
120 if (color_space == COLOR_SPACE_SRGB ||
121 color_space == COLOR_SPACE_XR_RGB ||
122 color_space == COLOR_SPACE_MSREF_SCRGB ||
123 color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
124 color_space == COLOR_SPACE_ADOBERGB ||
125 color_space == COLOR_SPACE_DCIP3 ||
126 color_space == COLOR_SPACE_DOLBYVISION)
127 ret = true;
128 return ret;
129 }
130
is_rgb_limited_type(enum dc_color_space color_space)131 static bool is_rgb_limited_type(
132 enum dc_color_space color_space)
133 {
134 bool ret = false;
135
136 if (color_space == COLOR_SPACE_SRGB_LIMITED ||
137 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
138 ret = true;
139 return ret;
140 }
141
is_ycbcr601_type(enum dc_color_space color_space)142 static bool is_ycbcr601_type(
143 enum dc_color_space color_space)
144 {
145 bool ret = false;
146
147 if (color_space == COLOR_SPACE_YCBCR601 ||
148 color_space == COLOR_SPACE_XV_YCC_601)
149 ret = true;
150 return ret;
151 }
152
is_ycbcr601_limited_type(enum dc_color_space color_space)153 static bool is_ycbcr601_limited_type(
154 enum dc_color_space color_space)
155 {
156 bool ret = false;
157
158 if (color_space == COLOR_SPACE_YCBCR601_LIMITED)
159 ret = true;
160 return ret;
161 }
162
is_ycbcr709_type(enum dc_color_space color_space)163 static bool is_ycbcr709_type(
164 enum dc_color_space color_space)
165 {
166 bool ret = false;
167
168 if (color_space == COLOR_SPACE_YCBCR709 ||
169 color_space == COLOR_SPACE_XV_YCC_709)
170 ret = true;
171 return ret;
172 }
173
is_ycbcr2020_type(enum dc_color_space color_space)174 static bool is_ycbcr2020_type(
175 enum dc_color_space color_space)
176 {
177 bool ret = false;
178
179 if (color_space == COLOR_SPACE_2020_YCBCR_LIMITED || color_space == COLOR_SPACE_2020_YCBCR_FULL)
180 ret = true;
181 return ret;
182 }
183
is_ycbcr709_limited_type(enum dc_color_space color_space)184 static bool is_ycbcr709_limited_type(
185 enum dc_color_space color_space)
186 {
187 bool ret = false;
188
189 if (color_space == COLOR_SPACE_YCBCR709_LIMITED)
190 ret = true;
191 return ret;
192 }
193
get_color_space_type(enum dc_color_space color_space)194 static enum dc_color_space_type get_color_space_type(enum dc_color_space color_space)
195 {
196 enum dc_color_space_type type = COLOR_SPACE_RGB_TYPE;
197
198 if (is_rgb_type(color_space))
199 type = COLOR_SPACE_RGB_TYPE;
200 else if (is_rgb_limited_type(color_space))
201 type = COLOR_SPACE_RGB_LIMITED_TYPE;
202 else if (is_ycbcr601_type(color_space))
203 type = COLOR_SPACE_YCBCR601_TYPE;
204 else if (is_ycbcr709_type(color_space))
205 type = COLOR_SPACE_YCBCR709_TYPE;
206 else if (is_ycbcr601_limited_type(color_space))
207 type = COLOR_SPACE_YCBCR601_LIMITED_TYPE;
208 else if (is_ycbcr709_limited_type(color_space))
209 type = COLOR_SPACE_YCBCR709_LIMITED_TYPE;
210 else if (is_ycbcr2020_type(color_space))
211 type = COLOR_SPACE_YCBCR2020_TYPE;
212 else if (color_space == COLOR_SPACE_YCBCR709)
213 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
214 else if (color_space == COLOR_SPACE_YCBCR709_BLACK)
215 type = COLOR_SPACE_YCBCR709_BLACK_TYPE;
216 return type;
217 }
218
find_color_matrix(enum dc_color_space color_space,uint32_t * array_size)219 const uint16_t *find_color_matrix(enum dc_color_space color_space,
220 uint32_t *array_size)
221 {
222 int i;
223 enum dc_color_space_type type;
224 const uint16_t *val = NULL;
225 int arr_size = NUM_ELEMENTS(output_csc_matrix);
226
227 type = get_color_space_type(color_space);
228 for (i = 0; i < arr_size; i++)
229 if (output_csc_matrix[i].color_space_type == type) {
230 val = output_csc_matrix[i].regval;
231 *array_size = 12;
232 break;
233 }
234
235 return val;
236 }
237
238
color_space_to_black_color(const struct dc * dc,enum dc_color_space colorspace,struct tg_color * black_color)239 void color_space_to_black_color(
240 const struct dc *dc,
241 enum dc_color_space colorspace,
242 struct tg_color *black_color)
243 {
244 switch (colorspace) {
245 case COLOR_SPACE_YCBCR601:
246 case COLOR_SPACE_YCBCR709:
247 case COLOR_SPACE_YCBCR709_BLACK:
248 case COLOR_SPACE_YCBCR601_LIMITED:
249 case COLOR_SPACE_YCBCR709_LIMITED:
250 case COLOR_SPACE_2020_YCBCR_LIMITED:
251 case COLOR_SPACE_2020_YCBCR_FULL:
252 *black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
253 break;
254
255 case COLOR_SPACE_SRGB_LIMITED:
256 *black_color =
257 black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
258 break;
259
260 /**
261 * Remove default and add case for all color space
262 * so when we forget to add new color space
263 * compiler will give a warning
264 */
265 case COLOR_SPACE_UNKNOWN:
266 case COLOR_SPACE_SRGB:
267 case COLOR_SPACE_XR_RGB:
268 case COLOR_SPACE_MSREF_SCRGB:
269 case COLOR_SPACE_XV_YCC_709:
270 case COLOR_SPACE_XV_YCC_601:
271 case COLOR_SPACE_2020_RGB_FULLRANGE:
272 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
273 case COLOR_SPACE_ADOBERGB:
274 case COLOR_SPACE_DCIP3:
275 case COLOR_SPACE_DISPLAYNATIVE:
276 case COLOR_SPACE_DOLBYVISION:
277 case COLOR_SPACE_APPCTRL:
278 case COLOR_SPACE_CUSTOMPOINTS:
279 /* fefault is sRGB black (full range). */
280 *black_color =
281 black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
282 /* default is sRGB black 0. */
283 break;
284 }
285 }
286
hwss_wait_for_blank_complete(struct timing_generator * tg)287 bool hwss_wait_for_blank_complete(
288 struct timing_generator *tg)
289 {
290 int counter;
291
292 /* Not applicable if the pipe is not primary, save 300ms of boot time */
293 if (!tg->funcs->is_blanked)
294 return true;
295 for (counter = 0; counter < 100; counter++) {
296 if (tg->funcs->is_blanked(tg))
297 break;
298
299 msleep(1);
300 }
301
302 if (counter == 100) {
303 dm_error("DC: failed to blank crtc!\n");
304 return false;
305 }
306
307 return true;
308 }
309
get_mpctree_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)310 void get_mpctree_visual_confirm_color(
311 struct pipe_ctx *pipe_ctx,
312 struct tg_color *color)
313 {
314 const struct tg_color pipe_colors[6] = {
315 {MAX_TG_COLOR_VALUE, 0, 0}, /* red */
316 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, /* orange */
317 {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
318 {0, MAX_TG_COLOR_VALUE, 0}, /* green */
319 {0, 0, MAX_TG_COLOR_VALUE}, /* blue */
320 {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, /* purple */
321 };
322
323 struct pipe_ctx *top_pipe = pipe_ctx;
324
325 while (top_pipe->top_pipe)
326 top_pipe = top_pipe->top_pipe;
327
328 *color = pipe_colors[top_pipe->pipe_idx];
329 }
330
get_surface_visual_confirm_color(const struct pipe_ctx * pipe_ctx,struct tg_color * color)331 void get_surface_visual_confirm_color(
332 const struct pipe_ctx *pipe_ctx,
333 struct tg_color *color)
334 {
335 uint32_t color_value = MAX_TG_COLOR_VALUE;
336
337 switch (pipe_ctx->plane_res.scl_data.format) {
338 case PIXEL_FORMAT_ARGB8888:
339 /* set border color to red */
340 color->color_r_cr = color_value;
341 if (pipe_ctx->plane_state->layer_index > 0) {
342 /* set border color to pink */
343 color->color_b_cb = color_value;
344 color->color_g_y = color_value * 0.5;
345 }
346 break;
347
348 case PIXEL_FORMAT_ARGB2101010:
349 /* set border color to blue */
350 color->color_b_cb = color_value;
351 if (pipe_ctx->plane_state->layer_index > 0) {
352 /* set border color to cyan */
353 color->color_g_y = color_value;
354 }
355 break;
356 case PIXEL_FORMAT_420BPP8:
357 /* set border color to green */
358 color->color_g_y = color_value;
359 break;
360 case PIXEL_FORMAT_420BPP10:
361 /* set border color to yellow */
362 color->color_g_y = color_value;
363 color->color_r_cr = color_value;
364 break;
365 case PIXEL_FORMAT_FP16:
366 /* set border color to white */
367 color->color_r_cr = color_value;
368 color->color_b_cb = color_value;
369 color->color_g_y = color_value;
370 if (pipe_ctx->plane_state->layer_index > 0) {
371 /* set border color to orange */
372 color->color_g_y = 0.22 * color_value;
373 color->color_b_cb = 0;
374 }
375 break;
376 default:
377 break;
378 }
379 }
380
get_hdr_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)381 void get_hdr_visual_confirm_color(
382 struct pipe_ctx *pipe_ctx,
383 struct tg_color *color)
384 {
385 uint32_t color_value = MAX_TG_COLOR_VALUE;
386 bool is_sdr = false;
387
388 /* Determine the overscan color based on the top-most (desktop) plane's context */
389 struct pipe_ctx *top_pipe_ctx = pipe_ctx;
390
391 while (top_pipe_ctx->top_pipe != NULL)
392 top_pipe_ctx = top_pipe_ctx->top_pipe;
393
394 switch (top_pipe_ctx->plane_res.scl_data.format) {
395 case PIXEL_FORMAT_ARGB2101010:
396 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
397 /* HDR10, ARGB2101010 - set border color to red */
398 color->color_r_cr = color_value;
399 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
400 /* FreeSync 2 ARGB2101010 - set border color to pink */
401 color->color_r_cr = color_value;
402 color->color_b_cb = color_value;
403 } else
404 is_sdr = true;
405 break;
406 case PIXEL_FORMAT_FP16:
407 if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
408 /* HDR10, FP16 - set border color to blue */
409 color->color_b_cb = color_value;
410 } else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
411 /* FreeSync 2 HDR - set border color to green */
412 color->color_g_y = color_value;
413 } else
414 is_sdr = true;
415 break;
416 default:
417 is_sdr = true;
418 break;
419 }
420
421 if (is_sdr) {
422 /* SDR - set border color to Gray */
423 color->color_r_cr = color_value/2;
424 color->color_b_cb = color_value/2;
425 color->color_g_y = color_value/2;
426 }
427 }
428
get_subvp_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)429 void get_subvp_visual_confirm_color(
430 struct pipe_ctx *pipe_ctx,
431 struct tg_color *color)
432 {
433 uint32_t color_value = MAX_TG_COLOR_VALUE;
434 if (pipe_ctx) {
435 switch (pipe_ctx->p_state_type) {
436 case P_STATE_SUB_VP:
437 color->color_r_cr = color_value;
438 color->color_g_y = 0;
439 color->color_b_cb = 0;
440 break;
441 case P_STATE_DRR_SUB_VP:
442 color->color_r_cr = 0;
443 color->color_g_y = color_value;
444 color->color_b_cb = 0;
445 break;
446 case P_STATE_V_BLANK_SUB_VP:
447 color->color_r_cr = 0;
448 color->color_g_y = 0;
449 color->color_b_cb = color_value;
450 break;
451 default:
452 break;
453 }
454 }
455 }
456
get_mclk_switch_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)457 void get_mclk_switch_visual_confirm_color(
458 struct pipe_ctx *pipe_ctx,
459 struct tg_color *color)
460 {
461 uint32_t color_value = MAX_TG_COLOR_VALUE;
462
463 if (pipe_ctx) {
464 switch (pipe_ctx->p_state_type) {
465 case P_STATE_V_BLANK:
466 color->color_r_cr = color_value;
467 color->color_g_y = color_value;
468 color->color_b_cb = 0;
469 break;
470 case P_STATE_FPO:
471 color->color_r_cr = 0;
472 color->color_g_y = color_value;
473 color->color_b_cb = color_value;
474 break;
475 case P_STATE_V_ACTIVE:
476 color->color_r_cr = color_value;
477 color->color_g_y = 0;
478 color->color_b_cb = color_value;
479 break;
480 case P_STATE_SUB_VP:
481 color->color_r_cr = color_value;
482 color->color_g_y = 0;
483 color->color_b_cb = 0;
484 break;
485 case P_STATE_DRR_SUB_VP:
486 color->color_r_cr = 0;
487 color->color_g_y = color_value;
488 color->color_b_cb = 0;
489 break;
490 case P_STATE_V_BLANK_SUB_VP:
491 color->color_r_cr = 0;
492 color->color_g_y = 0;
493 color->color_b_cb = color_value;
494 break;
495 default:
496 break;
497 }
498 }
499 }
500
set_p_state_switch_method(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)501 void set_p_state_switch_method(
502 struct dc *dc,
503 struct dc_state *context,
504 struct pipe_ctx *pipe_ctx)
505 {
506 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
507 bool enable_subvp;
508
509 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)
510 return;
511
512 pipe_ctx->p_state_type = P_STATE_UNKNOWN;
513 if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] !=
514 dm_dram_clock_change_unsupported) {
515 /* MCLK switching is supported */
516 if (!pipe_ctx->has_vactive_margin) {
517 /* In Vblank - yellow */
518 pipe_ctx->p_state_type = P_STATE_V_BLANK;
519
520 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
521 /* FPO + Vblank - cyan */
522 pipe_ctx->p_state_type = P_STATE_FPO;
523 }
524 } else {
525 /* In Vactive - pink */
526 pipe_ctx->p_state_type = P_STATE_V_ACTIVE;
527 }
528
529 /* SubVP */
530 enable_subvp = false;
531
532 for (int i = 0; i < dc->res_pool->pipe_count; i++) {
533 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
534
535 if (pipe->stream && dc_state_get_paired_subvp_stream(context, pipe->stream) &&
536 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {
537 /* SubVP enable - red */
538 pipe_ctx->p_state_type = P_STATE_SUB_VP;
539 enable_subvp = true;
540
541 if (pipe_ctx->stream == pipe->stream)
542 return;
543 break;
544 }
545 }
546
547 if (enable_subvp && dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_NONE) {
548 if (pipe_ctx->stream->allow_freesync == 1) {
549 /* SubVP enable and DRR on - green */
550 pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP;
551 } else {
552 /* SubVP enable and No DRR - blue */
553 pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP;
554 }
555 }
556 }
557 }
558
set_drr_and_clear_adjust_pending(struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream,struct drr_params * params)559 void set_drr_and_clear_adjust_pending(
560 struct pipe_ctx *pipe_ctx,
561 struct dc_stream_state *stream,
562 struct drr_params *params)
563 {
564 /* params can be null.*/
565 if (pipe_ctx && pipe_ctx->stream_res.tg &&
566 pipe_ctx->stream_res.tg->funcs->set_drr)
567 pipe_ctx->stream_res.tg->funcs->set_drr(
568 pipe_ctx->stream_res.tg, params);
569
570 if (stream)
571 stream->adjust.timing_adjust_pending = false;
572 }
573
get_fams2_visual_confirm_color(struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx,struct tg_color * color)574 void get_fams2_visual_confirm_color(
575 struct dc *dc,
576 struct dc_state *context,
577 struct pipe_ctx *pipe_ctx,
578 struct tg_color *color)
579 {
580 uint32_t color_value = MAX_TG_COLOR_VALUE;
581
582 if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)
583 return;
584
585 /* driver only handles visual confirm when FAMS2 is disabled */
586 if (!dc_state_is_fams2_in_use(dc, context)) {
587 /* when FAMS2 is disabled, all pipes are grey */
588 color->color_g_y = color_value / 2;
589 color->color_b_cb = color_value / 2;
590 color->color_r_cr = color_value / 2;
591 }
592 }
593
hwss_build_fast_sequence(struct dc * dc,struct dc_dmub_cmd * dc_dmub_cmd,unsigned int dmub_cmd_count,struct block_sequence block_sequence[],unsigned int * num_steps,struct pipe_ctx * pipe_ctx,struct dc_stream_status * stream_status,struct dc_state * context)594 void hwss_build_fast_sequence(struct dc *dc,
595 struct dc_dmub_cmd *dc_dmub_cmd,
596 unsigned int dmub_cmd_count,
597 struct block_sequence block_sequence[],
598 unsigned int *num_steps,
599 struct pipe_ctx *pipe_ctx,
600 struct dc_stream_status *stream_status,
601 struct dc_state *context)
602 {
603 struct dc_plane_state *plane = pipe_ctx->plane_state;
604 struct dc_stream_state *stream = pipe_ctx->stream;
605 struct dce_hwseq *hws = dc->hwseq;
606 struct pipe_ctx *current_pipe = NULL;
607 struct pipe_ctx *current_mpc_pipe = NULL;
608 unsigned int i = 0;
609
610 *num_steps = 0; // Initialize to 0
611
612 if (!plane || !stream)
613 return;
614
615 if (dc->hwss.wait_for_dcc_meta_propagation) {
616 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc;
617 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_ctx;
618 block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP;
619 (*num_steps)++;
620 }
621 if (dc->hwss.subvp_pipe_control_lock_fast) {
622 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
623 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true;
624 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
625 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
626 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
627 (*num_steps)++;
628 }
629 if (dc->hwss.fams2_global_control_lock_fast) {
630 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;
631 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = true;
632 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
633 block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST;
634 (*num_steps)++;
635 }
636 if (dc->hwss.pipe_control_lock) {
637 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
638 block_sequence[*num_steps].params.pipe_control_lock_params.lock = true;
639 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
640 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
641 (*num_steps)++;
642 }
643
644 for (i = 0; i < dmub_cmd_count; i++) {
645 block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx;
646 block_sequence[*num_steps].params.send_dmcub_cmd_params.cmd = &(dc_dmub_cmd[i].dmub_cmd);
647 block_sequence[*num_steps].params.send_dmcub_cmd_params.wait_type = dc_dmub_cmd[i].wait_type;
648 block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD;
649 (*num_steps)++;
650 }
651
652 current_pipe = pipe_ctx;
653 while (current_pipe) {
654 current_mpc_pipe = current_pipe;
655 while (current_mpc_pipe) {
656 if (current_mpc_pipe->plane_state) {
657 if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) {
658 block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe;
659 block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;
660 block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
661 (*num_steps)++;
662 }
663 if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {
664 block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;
665 block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;
666 block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;
667 block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
668 (*num_steps)++;
669 }
670 if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {
671 if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) &&
672 stream_status->mall_stream_config.type == SUBVP_MAIN) {
673 block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;
674 block_sequence[*num_steps].params.subvp_save_surf_addr.addr = ¤t_mpc_pipe->plane_state->address;
675 block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index;
676 block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
677 (*num_steps)++;
678 }
679
680 block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;
681 block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;
682 block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;
683 (*num_steps)++;
684 }
685
686 if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {
687 block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
688 block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;
689 block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;
690 block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
691 (*num_steps)++;
692 }
693
694 if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {
695 block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;
696 block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
697 (*num_steps)++;
698 }
699 if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) {
700 block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;
701 block_sequence[*num_steps].func = DPP_SETUP_DPP;
702 (*num_steps)++;
703 }
704 if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) {
705 block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;
706 block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
707 (*num_steps)++;
708 }
709 }
710 if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
711 block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
712 block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;
713 block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream;
714 block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
715 (*num_steps)++;
716 }
717
718 if (current_mpc_pipe->stream->update_flags.bits.out_csc) {
719 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc;
720 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
721 block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true;
722 block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR;
723 (*num_steps)++;
724
725 if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) {
726 block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc;
727 block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
728 block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix;
729 block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
730 block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC;
731 (*num_steps)++;
732 } else {
733 block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc;
734 block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst;
735 block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space;
736 block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
737 block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT;
738 (*num_steps)++;
739 }
740 }
741 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
742 }
743 current_pipe = current_pipe->next_odm_pipe;
744 }
745
746 if (dc->hwss.pipe_control_lock) {
747 block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc;
748 block_sequence[*num_steps].params.pipe_control_lock_params.lock = false;
749 block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx;
750 block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK;
751 (*num_steps)++;
752 }
753 if (dc->hwss.subvp_pipe_control_lock_fast) {
754 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc;
755 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false;
756 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip =
757 plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN;
758 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST;
759 (*num_steps)++;
760 }
761 if (dc->hwss.fams2_global_control_lock_fast) {
762 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc;
763 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = false;
764 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context);
765 block_sequence[*num_steps].func = DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST;
766 (*num_steps)++;
767 }
768
769 current_pipe = pipe_ctx;
770 while (current_pipe) {
771 current_mpc_pipe = current_pipe;
772
773 while (current_mpc_pipe) {
774 if (!current_mpc_pipe->bottom_pipe && !current_mpc_pipe->next_odm_pipe &&
775 current_mpc_pipe->stream && current_mpc_pipe->plane_state &&
776 current_mpc_pipe->plane_state->update_flags.bits.addr_update &&
777 !current_mpc_pipe->plane_state->skip_manual_trigger) {
778 block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe;
779 block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER;
780 (*num_steps)++;
781 }
782 current_mpc_pipe = current_mpc_pipe->bottom_pipe;
783 }
784 current_pipe = current_pipe->next_odm_pipe;
785 }
786 }
787
hwss_execute_sequence(struct dc * dc,struct block_sequence block_sequence[],int num_steps)788 void hwss_execute_sequence(struct dc *dc,
789 struct block_sequence block_sequence[],
790 int num_steps)
791 {
792 unsigned int i;
793 union block_sequence_params *params;
794 struct dce_hwseq *hws = dc->hwseq;
795
796 for (i = 0; i < num_steps; i++) {
797 params = &(block_sequence[i].params);
798 switch (block_sequence[i].func) {
799
800 case DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST:
801 dc->hwss.subvp_pipe_control_lock_fast(params);
802 break;
803 case OPTC_PIPE_CONTROL_LOCK:
804 dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc,
805 params->pipe_control_lock_params.pipe_ctx,
806 params->pipe_control_lock_params.lock);
807 break;
808 case HUBP_SET_FLIP_CONTROL_GSL:
809 dc->hwss.set_flip_control_gsl(params->set_flip_control_gsl_params.pipe_ctx,
810 params->set_flip_control_gsl_params.flip_immediate);
811 break;
812 case HUBP_PROGRAM_TRIPLEBUFFER:
813 dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc,
814 params->program_triplebuffer_params.pipe_ctx,
815 params->program_triplebuffer_params.enableTripleBuffer);
816 break;
817 case HUBP_UPDATE_PLANE_ADDR:
818 dc->hwss.update_plane_addr(params->update_plane_addr_params.dc,
819 params->update_plane_addr_params.pipe_ctx);
820 break;
821 case DPP_SET_INPUT_TRANSFER_FUNC:
822 hws->funcs.set_input_transfer_func(params->set_input_transfer_func_params.dc,
823 params->set_input_transfer_func_params.pipe_ctx,
824 params->set_input_transfer_func_params.plane_state);
825 break;
826 case DPP_PROGRAM_GAMUT_REMAP:
827 dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);
828 break;
829 case DPP_SETUP_DPP:
830 hwss_setup_dpp(params);
831 break;
832 case DPP_PROGRAM_BIAS_AND_SCALE:
833 hwss_program_bias_and_scale(params);
834 break;
835 case OPTC_PROGRAM_MANUAL_TRIGGER:
836 hwss_program_manual_trigger(params);
837 break;
838 case DPP_SET_OUTPUT_TRANSFER_FUNC:
839 hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc,
840 params->set_output_transfer_func_params.pipe_ctx,
841 params->set_output_transfer_func_params.stream);
842 break;
843 case MPC_UPDATE_VISUAL_CONFIRM:
844 dc->hwss.update_visual_confirm_color(params->update_visual_confirm_params.dc,
845 params->update_visual_confirm_params.pipe_ctx,
846 params->update_visual_confirm_params.mpcc_id);
847 break;
848 case MPC_POWER_ON_MPC_MEM_PWR:
849 hwss_power_on_mpc_mem_pwr(params);
850 break;
851 case MPC_SET_OUTPUT_CSC:
852 hwss_set_output_csc(params);
853 break;
854 case MPC_SET_OCSC_DEFAULT:
855 hwss_set_ocsc_default(params);
856 break;
857 case DMUB_SEND_DMCUB_CMD:
858 hwss_send_dmcub_cmd(params);
859 break;
860 case DMUB_SUBVP_SAVE_SURF_ADDR:
861 hwss_subvp_save_surf_addr(params);
862 break;
863 case HUBP_WAIT_FOR_DCC_META_PROP:
864 dc->hwss.wait_for_dcc_meta_propagation(
865 params->wait_for_dcc_meta_propagation_params.dc,
866 params->wait_for_dcc_meta_propagation_params.top_pipe_to_program);
867 break;
868 case DMUB_FAMS2_GLOBAL_CONTROL_LOCK_FAST:
869 dc->hwss.fams2_global_control_lock_fast(params);
870 break;
871 default:
872 ASSERT(false);
873 break;
874 }
875 }
876 }
877
hwss_send_dmcub_cmd(union block_sequence_params * params)878 void hwss_send_dmcub_cmd(union block_sequence_params *params)
879 {
880 struct dc_context *ctx = params->send_dmcub_cmd_params.ctx;
881 union dmub_rb_cmd *cmd = params->send_dmcub_cmd_params.cmd;
882 enum dm_dmub_wait_type wait_type = params->send_dmcub_cmd_params.wait_type;
883
884 dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type);
885 }
886
hwss_program_manual_trigger(union block_sequence_params * params)887 void hwss_program_manual_trigger(union block_sequence_params *params)
888 {
889 struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx;
890
891 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
892 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
893 }
894
hwss_setup_dpp(union block_sequence_params * params)895 void hwss_setup_dpp(union block_sequence_params *params)
896 {
897 struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx;
898 struct dpp *dpp = pipe_ctx->plane_res.dpp;
899 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
900
901 if (!plane_state)
902 return;
903
904 if (dpp && dpp->funcs->dpp_setup) {
905 // program the input csc
906 dpp->funcs->dpp_setup(dpp,
907 plane_state->format,
908 EXPANSION_MODE_ZERO,
909 plane_state->input_csc_color_matrix,
910 plane_state->color_space,
911 NULL);
912 }
913
914 if (dpp && dpp->funcs->set_cursor_matrix) {
915 dpp->funcs->set_cursor_matrix(dpp,
916 plane_state->color_space,
917 plane_state->cursor_csc_color_matrix);
918 }
919 }
920
hwss_program_bias_and_scale(union block_sequence_params * params)921 void hwss_program_bias_and_scale(union block_sequence_params *params)
922 {
923 struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx;
924 struct dpp *dpp = pipe_ctx->plane_res.dpp;
925 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
926 struct dc_bias_and_scale bns_params = plane_state->bias_and_scale;
927
928 //TODO :for CNVC set scale and bias registers if necessary
929 if (dpp->funcs->dpp_program_bias_and_scale) {
930 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
931 }
932 }
933
hwss_power_on_mpc_mem_pwr(union block_sequence_params * params)934 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params)
935 {
936 struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc;
937 int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id;
938 bool power_on = params->power_on_mpc_mem_pwr_params.power_on;
939
940 if (mpc->funcs->power_on_mpc_mem_pwr)
941 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on);
942 }
943
hwss_set_output_csc(union block_sequence_params * params)944 void hwss_set_output_csc(union block_sequence_params *params)
945 {
946 struct mpc *mpc = params->set_output_csc_params.mpc;
947 int opp_id = params->set_output_csc_params.opp_id;
948 const uint16_t *matrix = params->set_output_csc_params.regval;
949 enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode;
950
951 if (mpc->funcs->set_output_csc != NULL)
952 mpc->funcs->set_output_csc(mpc,
953 opp_id,
954 matrix,
955 ocsc_mode);
956 }
957
hwss_set_ocsc_default(union block_sequence_params * params)958 void hwss_set_ocsc_default(union block_sequence_params *params)
959 {
960 struct mpc *mpc = params->set_ocsc_default_params.mpc;
961 int opp_id = params->set_ocsc_default_params.opp_id;
962 enum dc_color_space colorspace = params->set_ocsc_default_params.color_space;
963 enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode;
964
965 if (mpc->funcs->set_ocsc_default != NULL)
966 mpc->funcs->set_ocsc_default(mpc,
967 opp_id,
968 colorspace,
969 ocsc_mode);
970 }
971
hwss_subvp_save_surf_addr(union block_sequence_params * params)972 void hwss_subvp_save_surf_addr(union block_sequence_params *params)
973 {
974 struct dc_dmub_srv *dc_dmub_srv = params->subvp_save_surf_addr.dc_dmub_srv;
975 const struct dc_plane_address *addr = params->subvp_save_surf_addr.addr;
976 uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index;
977
978 dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index);
979 }
980
get_surface_tile_visual_confirm_color(struct pipe_ctx * pipe_ctx,struct tg_color * color)981 void get_surface_tile_visual_confirm_color(
982 struct pipe_ctx *pipe_ctx,
983 struct tg_color *color)
984 {
985 uint32_t color_value = MAX_TG_COLOR_VALUE;
986 /* Determine the overscan color based on the bottom-most plane's context */
987 struct pipe_ctx *bottom_pipe_ctx = pipe_ctx;
988
989 while (bottom_pipe_ctx->bottom_pipe != NULL)
990 bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;
991
992 switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
993 case DC_SW_LINEAR:
994 /* LINEAR Surface - set border color to red */
995 color->color_r_cr = color_value;
996 break;
997 default:
998 break;
999 }
1000 }
1001
1002 /**
1003 * hwss_wait_for_all_blank_complete - wait for all active OPPs to finish pending blank
1004 * pattern updates
1005 *
1006 * @dc: [in] dc reference
1007 * @context: [in] hardware context in use
1008 */
hwss_wait_for_all_blank_complete(struct dc * dc,struct dc_state * context)1009 void hwss_wait_for_all_blank_complete(struct dc *dc,
1010 struct dc_state *context)
1011 {
1012 struct pipe_ctx *opp_head;
1013 struct dce_hwseq *hws = dc->hwseq;
1014 int i;
1015
1016 if (!hws->funcs.wait_for_blank_complete)
1017 return;
1018
1019 for (i = 0; i < MAX_PIPES; i++) {
1020 opp_head = &context->res_ctx.pipe_ctx[i];
1021
1022 if (!resource_is_pipe_type(opp_head, OPP_HEAD) ||
1023 dc_state_get_pipe_subvp_type(context, opp_head) == SUBVP_PHANTOM)
1024 continue;
1025
1026 hws->funcs.wait_for_blank_complete(opp_head->stream_res.opp);
1027 }
1028 }
1029
hwss_wait_for_odm_update_pending_complete(struct dc * dc,struct dc_state * context)1030 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, struct dc_state *context)
1031 {
1032 struct pipe_ctx *otg_master;
1033 struct timing_generator *tg;
1034 int i;
1035
1036 for (i = 0; i < MAX_PIPES; i++) {
1037 otg_master = &context->res_ctx.pipe_ctx[i];
1038 if (!resource_is_pipe_type(otg_master, OTG_MASTER) ||
1039 dc_state_get_pipe_subvp_type(context, otg_master) == SUBVP_PHANTOM)
1040 continue;
1041 tg = otg_master->stream_res.tg;
1042 if (tg->funcs->wait_odm_doublebuffer_pending_clear)
1043 tg->funcs->wait_odm_doublebuffer_pending_clear(tg);
1044 }
1045
1046 /* ODM update may require to reprogram blank pattern for each OPP */
1047 hwss_wait_for_all_blank_complete(dc, context);
1048 }
1049
hwss_wait_for_no_pipes_pending(struct dc * dc,struct dc_state * context)1050 void hwss_wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1051 {
1052 int i;
1053 for (i = 0; i < MAX_PIPES; i++) {
1054 int count = 0;
1055 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1056
1057 if (!pipe->plane_state || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM)
1058 continue;
1059
1060 /* Timeout 100 ms */
1061 while (count < 100000) {
1062 /* Must set to false to start with, due to OR in update function */
1063 pipe->plane_state->status.is_flip_pending = false;
1064 dc->hwss.update_pending_status(pipe);
1065 if (!pipe->plane_state->status.is_flip_pending)
1066 break;
1067 udelay(1);
1068 count++;
1069 }
1070 ASSERT(!pipe->plane_state->status.is_flip_pending);
1071 }
1072 }
1073
hwss_wait_for_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)1074 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
1075 {
1076 /*
1077 * This function calls HWSS to wait for any potentially double buffered
1078 * operations to complete. It should be invoked as a pre-amble prior
1079 * to full update programming before asserting any HW locks.
1080 */
1081 int pipe_idx;
1082 int opp_inst;
1083 int opp_count = dc->res_pool->res_cap->num_opp;
1084 struct hubp *hubp;
1085 int mpcc_inst;
1086 const struct pipe_ctx *pipe_ctx;
1087
1088 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
1089 pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx];
1090
1091 if (!pipe_ctx->stream)
1092 continue;
1093
1094 if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
1095 pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
1096
1097 hubp = pipe_ctx->plane_res.hubp;
1098 if (!hubp)
1099 continue;
1100
1101 mpcc_inst = hubp->inst;
1102 // MPCC inst is equal to pipe index in practice
1103 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1104 if ((dc->res_pool->opps[opp_inst] != NULL) &&
1105 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {
1106 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1107 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1108 break;
1109 }
1110 }
1111 }
1112 hwss_wait_for_odm_update_pending_complete(dc, dc_context);
1113 }
1114
hwss_process_outstanding_hw_updates(struct dc * dc,struct dc_state * dc_context)1115 void hwss_process_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_context)
1116 {
1117 /* wait for outstanding updates */
1118 hwss_wait_for_outstanding_hw_updates(dc, dc_context);
1119
1120 /* perform outstanding post update programming */
1121 if (dc->hwss.program_outstanding_updates)
1122 dc->hwss.program_outstanding_updates(dc, dc_context);
1123 }
1124