1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_HW_TYPES_H 27 #define DC_HW_TYPES_H 28 29 #include "os_types.h" 30 #include "fixed31_32.h" 31 #include "signal_types.h" 32 33 /****************************************************************************** 34 * Data types for Virtual HW Layer of DAL3. 35 * (see DAL3 design documents for HW Layer definition) 36 * 37 * The intended uses are: 38 * 1. Generation pseudocode sequences for HW programming. 39 * 2. Implementation of real HW programming by HW Sequencer of DAL3. 40 * 41 * Note: do *not* add any types which are *not* used for HW programming - this 42 * will ensure separation of Logic layer from HW layer. 43 ******************************************************************************/ 44 45 union large_integer { 46 struct { 47 uint32_t low_part; 48 int32_t high_part; 49 }; 50 51 struct { 52 uint32_t low_part; 53 int32_t high_part; 54 } u; 55 56 int64_t quad_part; 57 }; 58 59 #define PHYSICAL_ADDRESS_LOC union large_integer 60 61 enum dc_plane_addr_type { 62 PLN_ADDR_TYPE_GRAPHICS = 0, 63 PLN_ADDR_TYPE_3DLUT, 64 PLN_ADDR_TYPE_GRPH_STEREO, 65 PLN_ADDR_TYPE_VIDEO_PROGRESSIVE, 66 PLN_ADDR_TYPE_RGBEA 67 }; 68 69 struct dc_plane_address { 70 enum dc_plane_addr_type type; 71 bool tmz_surface; 72 union { 73 struct{ 74 PHYSICAL_ADDRESS_LOC addr; 75 PHYSICAL_ADDRESS_LOC cursor_cache_addr; 76 PHYSICAL_ADDRESS_LOC meta_addr; 77 union large_integer dcc_const_color; 78 } grph; 79 80 struct { 81 PHYSICAL_ADDRESS_LOC addr; 82 } lut3d; 83 84 /*stereo*/ 85 struct { 86 PHYSICAL_ADDRESS_LOC left_addr; 87 PHYSICAL_ADDRESS_LOC left_meta_addr; 88 union large_integer left_dcc_const_color; 89 90 PHYSICAL_ADDRESS_LOC right_addr; 91 PHYSICAL_ADDRESS_LOC right_meta_addr; 92 union large_integer right_dcc_const_color; 93 94 PHYSICAL_ADDRESS_LOC left_alpha_addr; 95 PHYSICAL_ADDRESS_LOC left_alpha_meta_addr; 96 union large_integer left_alpha_dcc_const_color; 97 98 PHYSICAL_ADDRESS_LOC right_alpha_addr; 99 PHYSICAL_ADDRESS_LOC right_alpha_meta_addr; 100 union large_integer right_alpha_dcc_const_color; 101 } grph_stereo; 102 103 /*video progressive*/ 104 struct { 105 PHYSICAL_ADDRESS_LOC luma_addr; 106 PHYSICAL_ADDRESS_LOC luma_meta_addr; 107 union large_integer luma_dcc_const_color; 108 109 PHYSICAL_ADDRESS_LOC chroma_addr; 110 PHYSICAL_ADDRESS_LOC chroma_meta_addr; 111 union large_integer chroma_dcc_const_color; 112 } video_progressive; 113 114 struct { 115 PHYSICAL_ADDRESS_LOC addr; 116 PHYSICAL_ADDRESS_LOC meta_addr; 117 union large_integer dcc_const_color; 118 119 PHYSICAL_ADDRESS_LOC alpha_addr; 120 PHYSICAL_ADDRESS_LOC alpha_meta_addr; 121 union large_integer alpha_dcc_const_color; 122 } rgbea; 123 }; 124 125 union large_integer page_table_base; 126 127 uint8_t vmid; 128 }; 129 130 struct dc_size { 131 int width; 132 int height; 133 }; 134 135 struct rect { 136 int x; 137 int y; 138 int width; 139 int height; 140 }; 141 142 struct plane_size { 143 /* Graphic surface pitch in pixels. 144 * In LINEAR_GENERAL mode, pitch 145 * is 32 pixel aligned. 146 */ 147 int surface_pitch; 148 int chroma_pitch; 149 struct rect surface_size; 150 struct rect chroma_size; 151 }; 152 153 struct dc_plane_dcc_param { 154 bool enable; 155 156 int meta_pitch; 157 bool independent_64b_blks; 158 uint8_t dcc_ind_blk; 159 160 int meta_pitch_c; 161 bool independent_64b_blks_c; 162 uint8_t dcc_ind_blk_c; 163 }; 164 165 /*Displayable pixel format in fb*/ 166 enum surface_pixel_format { 167 SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0, 168 /*TOBE REMOVED paletta 256 colors*/ 169 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS = 170 SURFACE_PIXEL_FORMAT_GRPH_BEGIN, 171 /*16 bpp*/ 172 SURFACE_PIXEL_FORMAT_GRPH_ARGB1555, 173 /*16 bpp*/ 174 SURFACE_PIXEL_FORMAT_GRPH_RGB565, 175 /*32 bpp*/ 176 SURFACE_PIXEL_FORMAT_GRPH_ARGB8888, 177 /*32 bpp swaped*/ 178 SURFACE_PIXEL_FORMAT_GRPH_ABGR8888, 179 180 SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010, 181 /*swaped*/ 182 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010, 183 /*TOBE REMOVED swaped, XR_BIAS has no differance 184 * for pixel layout than previous and we can 185 * delete this after discusion*/ 186 SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS, 187 /*64 bpp */ 188 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616, 189 /*swapped*/ 190 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616, 191 /*float*/ 192 SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F, 193 /*swaped & float*/ 194 SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F, 195 /*grow graphics here if necessary */ 196 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX, 197 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX, 198 SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT, 199 SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT, 200 SURFACE_PIXEL_FORMAT_GRPH_RGBE, 201 SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA, 202 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 203 SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr = 204 SURFACE_PIXEL_FORMAT_VIDEO_BEGIN, 205 SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb, 206 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr, 207 SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb, 208 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, 209 SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010 = 210 SURFACE_PIXEL_FORMAT_SUBSAMPLE_END, 211 SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102, 212 SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888, 213 SURFACE_PIXEL_FORMAT_INVALID 214 215 /*grow 444 video here if necessary */ 216 }; 217 218 219 220 /* Pixel format */ 221 enum pixel_format { 222 /*graph*/ 223 PIXEL_FORMAT_UNINITIALIZED, 224 PIXEL_FORMAT_INDEX8, 225 PIXEL_FORMAT_RGB565, 226 PIXEL_FORMAT_ARGB8888, 227 PIXEL_FORMAT_ARGB2101010, 228 PIXEL_FORMAT_ARGB2101010_XRBIAS, 229 PIXEL_FORMAT_FP16, 230 /*video*/ 231 PIXEL_FORMAT_420BPP8, 232 PIXEL_FORMAT_420BPP10, 233 /*end of pixel format definition*/ 234 PIXEL_FORMAT_INVALID, 235 236 PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8, 237 PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16, 238 PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8, 239 PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10, 240 PIXEL_FORMAT_UNKNOWN 241 }; 242 243 /* 244 * This structure holds a surface address. There could be multiple addresses 245 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 246 * as frame durations and DCC format can also be set. 247 */ 248 #define DC_MAX_DIRTY_RECTS 3 249 struct dc_flip_addrs { 250 struct dc_plane_address address; 251 unsigned long long flip_timestamp_in_us; 252 bool flip_immediate; 253 /* TODO: add flip duration for FreeSync */ 254 bool triplebuffer_flips; 255 unsigned int dirty_rect_count; 256 struct rect dirty_rects[DC_MAX_DIRTY_RECTS]; 257 }; 258 259 enum tile_split_values { 260 DC_DISPLAY_MICRO_TILING = 0x0, 261 DC_THIN_MICRO_TILING = 0x1, 262 DC_DEPTH_MICRO_TILING = 0x2, 263 DC_ROTATED_MICRO_TILING = 0x3, 264 }; 265 266 enum tripleBuffer_enable { 267 DC_TRIPLEBUFFER_DISABLE = 0x0, 268 DC_TRIPLEBUFFER_ENABLE = 0x1, 269 }; 270 enum tile_split_values_new { 271 DC_SURF_TILE_SPLIT_1KB = 0x4, 272 }; 273 274 /* TODO: These values come from hardware spec. We need to readdress this 275 * if they ever change. 276 */ 277 enum array_mode_values { 278 DC_ARRAY_LINEAR_GENERAL = 0, 279 DC_ARRAY_LINEAR_ALLIGNED, 280 DC_ARRAY_1D_TILED_THIN1, 281 DC_ARRAY_1D_TILED_THICK, 282 DC_ARRAY_2D_TILED_THIN1, 283 DC_ARRAY_PRT_TILED_THIN1, 284 DC_ARRAY_PRT_2D_TILED_THIN1, 285 DC_ARRAY_2D_TILED_THICK, 286 DC_ARRAY_2D_TILED_X_THICK, 287 DC_ARRAY_PRT_TILED_THICK, 288 DC_ARRAY_PRT_2D_TILED_THICK, 289 DC_ARRAY_PRT_3D_TILED_THIN1, 290 DC_ARRAY_3D_TILED_THIN1, 291 DC_ARRAY_3D_TILED_THICK, 292 DC_ARRAY_3D_TILED_X_THICK, 293 DC_ARRAY_PRT_3D_TILED_THICK, 294 }; 295 296 enum tile_mode_values { 297 DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 298 DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 299 }; 300 301 enum swizzle_mode_values { 302 DC_SW_LINEAR = 0, 303 DC_SW_256B_S = 1, 304 DC_SW_256_D = 2, 305 DC_SW_256_R = 3, 306 DC_SW_4KB_S = 5, 307 DC_SW_4KB_D = 6, 308 DC_SW_4KB_R = 7, 309 DC_SW_64KB_S = 9, 310 DC_SW_64KB_D = 10, 311 DC_SW_64KB_R = 11, 312 DC_SW_VAR_S = 13, 313 DC_SW_VAR_D = 14, 314 DC_SW_VAR_R = 15, 315 DC_SW_64KB_S_T = 17, 316 DC_SW_64KB_D_T = 18, 317 DC_SW_4KB_S_X = 21, 318 DC_SW_4KB_D_X = 22, 319 DC_SW_4KB_R_X = 23, 320 DC_SW_64KB_S_X = 25, 321 DC_SW_64KB_D_X = 26, 322 DC_SW_64KB_R_X = 27, 323 DC_SW_VAR_S_X = 29, 324 DC_SW_VAR_D_X = 30, 325 DC_SW_VAR_R_X = 31, 326 DC_SW_MAX = 32, 327 DC_SW_UNKNOWN = DC_SW_MAX 328 }; 329 330 // Definition of swizzle modes with addr3 ASICs 331 enum swizzle_mode_addr3_values { 332 DC_ADDR3_SW_LINEAR = 0, 333 DC_ADDR3_SW_256B_2D = 1, 334 DC_ADDR3_SW_4KB_2D = 2, 335 DC_ADDR3_SW_64KB_2D = 3, 336 DC_ADDR3_SW_256KB_2D = 4, 337 DC_ADDR3_SW_4KB_3D = 5, 338 DC_ADDR3_SW_64KB_3D = 6, 339 DC_ADDR3_SW_256KB_3D = 7, 340 DC_ADDR3_SW_MAX = 8, 341 DC_ADDR3_SW_UNKNOWN = DC_ADDR3_SW_MAX 342 }; 343 344 union dc_tiling_info { 345 346 struct { 347 /* Specifies the number of memory banks for tiling 348 * purposes. 349 * Only applies to 2D and 3D tiling modes. 350 * POSSIBLE VALUES: 2,4,8,16 351 */ 352 unsigned int num_banks; 353 /* Specifies the number of tiles in the x direction 354 * to be incorporated into the same bank. 355 * Only applies to 2D and 3D tiling modes. 356 * POSSIBLE VALUES: 1,2,4,8 357 */ 358 unsigned int bank_width; 359 unsigned int bank_width_c; 360 /* Specifies the number of tiles in the y direction to 361 * be incorporated into the same bank. 362 * Only applies to 2D and 3D tiling modes. 363 * POSSIBLE VALUES: 1,2,4,8 364 */ 365 unsigned int bank_height; 366 unsigned int bank_height_c; 367 /* Specifies the macro tile aspect ratio. Only applies 368 * to 2D and 3D tiling modes. 369 */ 370 unsigned int tile_aspect; 371 unsigned int tile_aspect_c; 372 /* Specifies the number of bytes that will be stored 373 * contiguously for each tile. 374 * If the tile data requires more storage than this 375 * amount, it is split into multiple slices. 376 * This field must not be larger than 377 * GB_ADDR_CONFIG.DRAM_ROW_SIZE. 378 * Only applies to 2D and 3D tiling modes. 379 * For color render targets, TILE_SPLIT >= 256B. 380 */ 381 enum tile_split_values tile_split; 382 enum tile_split_values tile_split_c; 383 /* Specifies the addressing within a tile. 384 * 0x0 - DISPLAY_MICRO_TILING 385 * 0x1 - THIN_MICRO_TILING 386 * 0x2 - DEPTH_MICRO_TILING 387 * 0x3 - ROTATED_MICRO_TILING 388 */ 389 enum tile_mode_values tile_mode; 390 enum tile_mode_values tile_mode_c; 391 /* Specifies the number of pipes and how they are 392 * interleaved in the surface. 393 * Refer to memory addressing document for complete 394 * details and constraints. 395 */ 396 unsigned int pipe_config; 397 /* Specifies the tiling mode of the surface. 398 * THIN tiles use an 8x8x1 tile size. 399 * THICK tiles use an 8x8x4 tile size. 400 * 2D tiling modes rotate banks for successive Z slices 401 * 3D tiling modes rotate pipes and banks for Z slices 402 * Refer to memory addressing document for complete 403 * details and constraints. 404 */ 405 enum array_mode_values array_mode; 406 } gfx8; 407 408 struct { 409 enum swizzle_mode_values swizzle; 410 unsigned int num_pipes; 411 unsigned int max_compressed_frags; 412 unsigned int pipe_interleave; 413 414 unsigned int num_banks; 415 unsigned int num_shader_engines; 416 unsigned int num_rb_per_se; 417 bool shaderEnable; 418 419 bool meta_linear; 420 bool rb_aligned; 421 bool pipe_aligned; 422 unsigned int num_pkrs; 423 } gfx9;/*gfx9, gfx10 and above*/ 424 struct { 425 enum swizzle_mode_addr3_values swizzle; 426 } gfx_addr3;/*gfx with addr3 and above*/ 427 }; 428 429 /* Rotation angle */ 430 enum dc_rotation_angle { 431 ROTATION_ANGLE_0 = 0, 432 ROTATION_ANGLE_90, 433 ROTATION_ANGLE_180, 434 ROTATION_ANGLE_270, 435 ROTATION_ANGLE_COUNT 436 }; 437 438 enum dc_scan_direction { 439 SCAN_DIRECTION_UNKNOWN = 0, 440 SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */ 441 SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */ 442 }; 443 444 /** 445 * struct dc_cursor_position: Hardware cursor data. 446 * 447 * This struct keeps the action information related to the cursor that will be 448 * sent and received from our DC core. 449 */ 450 struct dc_cursor_position { 451 /** 452 * @x: It represents the top left abscissa coordinate of the cursor. 453 */ 454 uint32_t x; 455 456 /** 457 * @y: It is the top ordinate of the cursor coordinate. 458 */ 459 uint32_t y; 460 461 /** 462 * @x_hotspot: Define the abscissa point where mouse click happens. 463 */ 464 uint32_t x_hotspot; 465 466 /** 467 * @y_hotspot: Define the ordinate point where mouse click happens. 468 */ 469 uint32_t y_hotspot; 470 471 /** 472 * @enable: This parameter indicates whether hardware cursor should be 473 * enabled. 474 */ 475 bool enable; 476 477 /** 478 * @translate_by_source: Translate cursor x/y by the source rectangle 479 * for each plane. 480 */ 481 bool translate_by_source; 482 }; 483 484 struct dc_cursor_mi_param { 485 unsigned int pixel_clk_khz; 486 unsigned int ref_clk_khz; 487 struct rect viewport; 488 struct rect recout; 489 struct fixed31_32 h_scale_ratio; 490 struct fixed31_32 v_scale_ratio; 491 enum dc_rotation_angle rotation; 492 bool mirror; 493 struct dc_stream_state *stream; 494 }; 495 496 /* IPP related types */ 497 498 enum { 499 GAMMA_RGB_256_ENTRIES = 256, 500 GAMMA_RGB_FLOAT_1024_ENTRIES = 1024, 501 GAMMA_CS_TFM_1D_ENTRIES = 4096, 502 GAMMA_CUSTOM_ENTRIES = 4096, 503 GAMMA_MAX_ENTRIES = 4096 504 }; 505 506 enum dc_gamma_type { 507 GAMMA_RGB_256 = 1, 508 GAMMA_RGB_FLOAT_1024 = 2, 509 GAMMA_CS_TFM_1D = 3, 510 GAMMA_CUSTOM = 4, 511 }; 512 513 struct dc_csc_transform { 514 uint16_t matrix[12]; 515 bool enable_adjustment; 516 }; 517 518 struct dc_rgb_fixed { 519 struct fixed31_32 red; 520 struct fixed31_32 green; 521 struct fixed31_32 blue; 522 }; 523 524 struct dc_gamma { 525 struct kref refcount; 526 enum dc_gamma_type type; 527 unsigned int num_entries; 528 529 struct dc_gamma_entries { 530 struct fixed31_32 red[GAMMA_MAX_ENTRIES]; 531 struct fixed31_32 green[GAMMA_MAX_ENTRIES]; 532 struct fixed31_32 blue[GAMMA_MAX_ENTRIES]; 533 } entries; 534 535 /* private to DC core */ 536 struct dc_context *ctx; 537 538 /* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT. 539 * is_logical_identity indicates the given gamma ramp regardless of type is identity. 540 */ 541 bool is_identity; 542 }; 543 544 /* Used by both ipp amd opp functions*/ 545 /* TODO: to be consolidated with enum color_space */ 546 547 /** 548 * enum dc_cursor_color_format - DC cursor programming mode 549 * 550 * This enum is for programming CURSOR_MODE register field. What this register 551 * should be programmed to depends on OS requested cursor shape flags and what 552 * we stored in the cursor surface. 553 */ 554 enum dc_cursor_color_format { 555 CURSOR_MODE_MONO, 556 CURSOR_MODE_COLOR_1BIT_AND, 557 CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA, 558 CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA, 559 CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED, 560 CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED 561 }; 562 563 /* 564 * This is all the parameters required by DAL in order to update the cursor 565 * attributes, including the new cursor image surface address, size, hotspot 566 * location, color format, etc. 567 */ 568 569 union dc_cursor_attribute_flags { 570 struct { 571 uint32_t ENABLE_MAGNIFICATION:1; 572 uint32_t INVERSE_TRANSPARENT_CLAMPING:1; 573 uint32_t HORIZONTAL_MIRROR:1; 574 uint32_t VERTICAL_MIRROR:1; 575 uint32_t INVERT_PIXEL_DATA:1; 576 uint32_t ZERO_EXPANSION:1; 577 uint32_t MIN_MAX_INVERT:1; 578 uint32_t ENABLE_CURSOR_DEGAMMA:1; 579 uint32_t RESERVED:24; 580 } bits; 581 uint32_t value; 582 }; 583 584 struct dc_cursor_attributes { 585 /** 586 * @address: This field represents the framebuffer address associated 587 * with the cursor. It is important to highlight that this address is 588 * divided into a high and low parts. 589 */ 590 PHYSICAL_ADDRESS_LOC address; 591 592 /** 593 * @pitch: Cursor line stride. 594 */ 595 uint32_t pitch; 596 597 /** 598 * @width: Width should correspond to cursor surface width. 599 */ 600 uint32_t width; 601 /** 602 * @heigh: Height should correspond to cursor surface heigh. 603 */ 604 uint32_t height; 605 606 /** 607 * @color_format: DC cursor programming mode. 608 */ 609 enum dc_cursor_color_format color_format; 610 /** 611 * @sdr_white_level: Boosting (SDR) cursor in HDR mode. 612 */ 613 uint32_t sdr_white_level; 614 615 /** 616 * @rotation_angle: In case we support HW Cursor rotation in the future 617 */ 618 enum dc_rotation_angle rotation_angle; 619 620 union dc_cursor_attribute_flags attribute_flags; 621 }; 622 623 struct dpp_cursor_attributes { 624 int bias; 625 int scale; 626 }; 627 628 /* OPP */ 629 630 enum dc_color_space { 631 COLOR_SPACE_UNKNOWN, 632 COLOR_SPACE_SRGB, 633 COLOR_SPACE_XR_RGB, 634 COLOR_SPACE_SRGB_LIMITED, 635 COLOR_SPACE_MSREF_SCRGB, 636 COLOR_SPACE_YCBCR601, 637 COLOR_SPACE_YCBCR709, 638 COLOR_SPACE_XV_YCC_709, 639 COLOR_SPACE_XV_YCC_601, 640 COLOR_SPACE_YCBCR601_LIMITED, 641 COLOR_SPACE_YCBCR709_LIMITED, 642 COLOR_SPACE_2020_RGB_FULLRANGE, 643 COLOR_SPACE_2020_RGB_LIMITEDRANGE, 644 COLOR_SPACE_2020_YCBCR_LIMITED, 645 COLOR_SPACE_2020_YCBCR_FULL, 646 COLOR_SPACE_ADOBERGB, 647 COLOR_SPACE_DCIP3, 648 COLOR_SPACE_DISPLAYNATIVE, 649 COLOR_SPACE_DOLBYVISION, 650 COLOR_SPACE_APPCTRL, 651 COLOR_SPACE_CUSTOMPOINTS, 652 COLOR_SPACE_YCBCR709_BLACK, 653 COLOR_SPACE_2020_YCBCR = COLOR_SPACE_2020_YCBCR_LIMITED, 654 }; 655 656 enum dc_dither_option { 657 DITHER_OPTION_DEFAULT, 658 DITHER_OPTION_DISABLE, 659 DITHER_OPTION_FM6, 660 DITHER_OPTION_FM8, 661 DITHER_OPTION_FM10, 662 DITHER_OPTION_SPATIAL6_FRAME_RANDOM, 663 DITHER_OPTION_SPATIAL8_FRAME_RANDOM, 664 DITHER_OPTION_SPATIAL10_FRAME_RANDOM, 665 DITHER_OPTION_SPATIAL6, 666 DITHER_OPTION_SPATIAL8, 667 DITHER_OPTION_SPATIAL10, 668 DITHER_OPTION_TRUN6, 669 DITHER_OPTION_TRUN8, 670 DITHER_OPTION_TRUN10, 671 DITHER_OPTION_TRUN10_SPATIAL8, 672 DITHER_OPTION_TRUN10_SPATIAL6, 673 DITHER_OPTION_TRUN10_FM8, 674 DITHER_OPTION_TRUN10_FM6, 675 DITHER_OPTION_TRUN10_SPATIAL8_FM6, 676 DITHER_OPTION_SPATIAL10_FM8, 677 DITHER_OPTION_SPATIAL10_FM6, 678 DITHER_OPTION_TRUN8_SPATIAL6, 679 DITHER_OPTION_TRUN8_FM6, 680 DITHER_OPTION_SPATIAL8_FM6, 681 DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6, 682 DITHER_OPTION_INVALID 683 }; 684 685 enum dc_quantization_range { 686 QUANTIZATION_RANGE_UNKNOWN, 687 QUANTIZATION_RANGE_FULL, 688 QUANTIZATION_RANGE_LIMITED 689 }; 690 691 enum dc_dynamic_expansion { 692 DYN_EXPANSION_AUTO, 693 DYN_EXPANSION_DISABLE 694 }; 695 696 /* XFM */ 697 698 /* used in struct dc_plane_state */ 699 struct scaling_taps { 700 uint32_t v_taps; 701 uint32_t h_taps; 702 uint32_t v_taps_c; 703 uint32_t h_taps_c; 704 bool integer_scaling; 705 }; 706 707 enum dc_timing_standard { 708 DC_TIMING_STANDARD_UNDEFINED, 709 DC_TIMING_STANDARD_DMT, 710 DC_TIMING_STANDARD_GTF, 711 DC_TIMING_STANDARD_CVT, 712 DC_TIMING_STANDARD_CVT_RB, 713 DC_TIMING_STANDARD_CEA770, 714 DC_TIMING_STANDARD_CEA861, 715 DC_TIMING_STANDARD_HDMI, 716 DC_TIMING_STANDARD_TV_NTSC, 717 DC_TIMING_STANDARD_TV_NTSC_J, 718 DC_TIMING_STANDARD_TV_PAL, 719 DC_TIMING_STANDARD_TV_PAL_M, 720 DC_TIMING_STANDARD_TV_PAL_CN, 721 DC_TIMING_STANDARD_TV_SECAM, 722 DC_TIMING_STANDARD_EXPLICIT, 723 /*!< For explicit timings from EDID, VBIOS, etc.*/ 724 DC_TIMING_STANDARD_USER_OVERRIDE, 725 /*!< For mode timing override by user*/ 726 DC_TIMING_STANDARD_MAX 727 }; 728 729 enum dc_color_depth { 730 COLOR_DEPTH_UNDEFINED, 731 COLOR_DEPTH_666, 732 COLOR_DEPTH_888, 733 COLOR_DEPTH_101010, 734 COLOR_DEPTH_121212, 735 COLOR_DEPTH_141414, 736 COLOR_DEPTH_161616, 737 COLOR_DEPTH_999, 738 COLOR_DEPTH_111111, 739 COLOR_DEPTH_COUNT 740 }; 741 742 enum dc_pixel_encoding { 743 PIXEL_ENCODING_UNDEFINED, 744 PIXEL_ENCODING_RGB, 745 PIXEL_ENCODING_YCBCR422, 746 PIXEL_ENCODING_YCBCR444, 747 PIXEL_ENCODING_YCBCR420, 748 PIXEL_ENCODING_COUNT 749 }; 750 751 enum dc_aspect_ratio { 752 ASPECT_RATIO_NO_DATA, 753 ASPECT_RATIO_4_3, 754 ASPECT_RATIO_16_9, 755 ASPECT_RATIO_64_27, 756 ASPECT_RATIO_256_135, 757 ASPECT_RATIO_FUTURE 758 }; 759 760 enum scanning_type { 761 SCANNING_TYPE_NODATA = 0, 762 SCANNING_TYPE_OVERSCAN, 763 SCANNING_TYPE_UNDERSCAN, 764 SCANNING_TYPE_FUTURE, 765 SCANNING_TYPE_UNDEFINED 766 }; 767 768 struct dc_crtc_timing_flags { 769 uint32_t INTERLACE :1; 770 uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1, 771 it is positive polarity --reversed with dal1 or video bios define*/ 772 uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1, 773 it is positive polarity --reversed with dal1 or video bios define*/ 774 775 uint32_t HORZ_COUNT_BY_TWO:1; 776 777 uint32_t EXCLUSIVE_3D :1; /* if this bit set, 778 timing can be driven in 3D format only 779 and there is no corresponding 2D timing*/ 780 uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity 781 (right eye = '1', left eye = '0') */ 782 uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled 783 when mixed into 3D image. 0 - means summation (3D timing is doubled)*/ 784 uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View, 785 because corresponding 2D timing also present in the list*/ 786 uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing 787 and we want to match priority of corresponding 3D timing*/ 788 uint32_t Y_ONLY :1; 789 790 uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */ 791 uint32_t DTD_COUNTER :5; /* values 1 to 16 */ 792 793 uint32_t FORCE_HDR :1; 794 795 /* HDMI 2.0 - Support scrambling for TMDS character 796 * rates less than or equal to 340Mcsc */ 797 uint32_t LTE_340MCSC_SCRAMBLE:1; 798 799 uint32_t DSC : 1; /* Use DSC with this timing */ 800 uint32_t VBLANK_SYNCHRONIZABLE: 1; 801 }; 802 803 enum dc_timing_3d_format { 804 TIMING_3D_FORMAT_NONE, 805 TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/ 806 TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/ 807 TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/ 808 /* for active DP-HDMI dongle*/ 809 TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/ 810 TIMING_3D_FORMAT_HW_FRAME_PACKING, 811 TIMING_3D_FORMAT_SW_FRAME_PACKING, 812 TIMING_3D_FORMAT_ROW_INTERLEAVE, 813 TIMING_3D_FORMAT_COLUMN_INTERLEAVE, 814 TIMING_3D_FORMAT_PIXEL_INTERLEAVE, 815 TIMING_3D_FORMAT_SIDE_BY_SIDE, 816 TIMING_3D_FORMAT_TOP_AND_BOTTOM, 817 TIMING_3D_FORMAT_SBS_SW_PACKED, 818 /* Side-by-side, packed by application/driver into 2D frame*/ 819 TIMING_3D_FORMAT_TB_SW_PACKED, 820 /* Top-and-bottom, packed by application/driver into 2D frame*/ 821 822 TIMING_3D_FORMAT_MAX, 823 }; 824 825 #define DC_DSC_QP_SET_SIZE 15 826 #define DC_DSC_RC_BUF_THRESH_SIZE 14 827 struct dc_dsc_rc_params_override { 828 int32_t rc_model_size; 829 int32_t rc_buf_thresh[DC_DSC_RC_BUF_THRESH_SIZE]; 830 int32_t rc_minqp[DC_DSC_QP_SET_SIZE]; 831 int32_t rc_maxqp[DC_DSC_QP_SET_SIZE]; 832 int32_t rc_offset[DC_DSC_QP_SET_SIZE]; 833 834 int32_t rc_tgt_offset_hi; 835 int32_t rc_tgt_offset_lo; 836 int32_t rc_edge_factor; 837 int32_t rc_quant_incr_limit0; 838 int32_t rc_quant_incr_limit1; 839 840 int32_t initial_fullness_offset; 841 int32_t initial_delay; 842 843 int32_t flatness_min_qp; 844 int32_t flatness_max_qp; 845 int32_t flatness_det_thresh; 846 }; 847 848 struct dc_dsc_config { 849 uint32_t num_slices_h; /* Number of DSC slices - horizontal */ 850 uint32_t num_slices_v; /* Number of DSC slices - vertical */ 851 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 852 bool block_pred_enable; /* DSC block prediction enable */ 853 uint32_t linebuf_depth; /* DSC line buffer depth */ 854 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ 855 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ 856 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 857 bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */ 858 bool is_dp; /* indicate if DSC is applied based on DP's capability */ 859 uint32_t mst_pbn; /* pbn of display on dsc mst hub */ 860 const struct dc_dsc_rc_params_override *rc_params_ovrd; /* DM owned memory. If not NULL, apply custom dsc rc params */ 861 }; 862 863 /** 864 * struct dc_crtc_timing - Timing parameters used to configure DCN blocks 865 * 866 * DCN provides multiple signals and parameters that can be used to adjust 867 * timing parameters, this struct aggregate multiple of these values for easy 868 * access. In this struct, fields prefixed with h_* are related to horizontal 869 * timing, and v_* to vertical timing. Keep in mind that when we talk about 870 * vertical timings, the values, in general, are described in the number of 871 * lines; on the other hand, the horizontal values are in pixels. 872 */ 873 struct dc_crtc_timing { 874 /** 875 * @h_total: The total number of pixels from the rising edge of HSync 876 * until the rising edge of the current HSync. 877 */ 878 uint32_t h_total; 879 880 /** 881 * @h_border_left: The black pixels related to the left border 882 */ 883 uint32_t h_border_left; 884 885 /** 886 * @h_addressable: It is the range of pixels displayed horizontally. 887 * For example, if the display resolution is 3840@2160, the horizontal 888 * addressable area is 3840. 889 */ 890 uint32_t h_addressable; 891 892 /** 893 * @h_border_right: The black pixels related to the right border 894 */ 895 uint32_t h_border_right; 896 897 /** 898 * @h_front_porch: Period (in pixels) between HBlank start and the 899 * rising edge of HSync. 900 */ 901 uint32_t h_front_porch; 902 903 /** 904 * @h_sync_width: HSync duration in pixels. 905 */ 906 uint32_t h_sync_width; 907 908 /** 909 * @v_total: It is the total number of lines from the rising edge of 910 * the previous VSync until the rising edge of the current VSync. 911 * 912 * |--------------------------| 913 * +-+ V_TOTAL +-+ 914 * | | | | 915 * VSync ---+ +--------- // -----------+ +--- 916 */ 917 uint32_t v_total; 918 919 /** 920 * @v_border_top: The black border on the top. 921 */ 922 uint32_t v_border_top; 923 924 /** 925 * @v_addressable: It is the range of the scanout at which the 926 * framebuffer is displayed. For example, if the display resolution is 927 * 3840@2160, the addressable area is 2160 lines, or if the resolution 928 * is 1920x1080, the addressable area is 1080 lines. 929 */ 930 uint32_t v_addressable; 931 932 /** 933 * @v_border_bottom: The black border on the bottom. 934 */ 935 uint32_t v_border_bottom; 936 937 /** 938 * @v_front_porch: Period (in lines) between VBlank start and rising 939 * edge of VSync. 940 * +-+ 941 * VSync | | 942 * ----------+ +--------... 943 * +------------------... 944 * VBlank | 945 * --+ 946 * |-------| 947 * v_front_porch 948 */ 949 uint32_t v_front_porch; 950 951 /** 952 * @v_sync_width: VSync signal width in lines. 953 */ 954 uint32_t v_sync_width; 955 956 /** 957 * @pix_clk_100hz: Pipe pixel precision 958 * 959 * This field is used to communicate pixel clocks with 100 Hz accuracy 960 * from dc_crtc_timing to BIOS command table. 961 */ 962 uint32_t pix_clk_100hz; 963 964 uint32_t min_refresh_in_uhz; 965 966 uint32_t vic; 967 uint32_t hdmi_vic; 968 uint32_t rid; 969 uint32_t fr_index; 970 uint32_t frl_uncompressed_video_bandwidth_in_kbps; 971 enum dc_timing_3d_format timing_3d_format; 972 enum dc_color_depth display_color_depth; 973 enum dc_pixel_encoding pixel_encoding; 974 enum dc_aspect_ratio aspect_ratio; 975 enum scanning_type scan_type; 976 977 struct dc_crtc_timing_flags flags; 978 uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ 979 struct dc_dsc_config dsc_cfg; 980 }; 981 982 enum trigger_delay { 983 TRIGGER_DELAY_NEXT_PIXEL = 0, 984 TRIGGER_DELAY_NEXT_LINE, 985 }; 986 987 enum crtc_event { 988 CRTC_EVENT_VSYNC_RISING = 0, 989 CRTC_EVENT_VSYNC_FALLING 990 }; 991 992 struct crtc_trigger_info { 993 bool enabled; 994 struct dc_stream_state *event_source; 995 enum crtc_event event; 996 enum trigger_delay delay; 997 }; 998 999 struct dc_crtc_timing_adjust { 1000 uint32_t v_total_min; 1001 uint32_t v_total_max; 1002 uint32_t v_total_mid; 1003 uint32_t v_total_mid_frame_num; 1004 uint32_t allow_otg_v_count_halt; 1005 uint8_t timing_adjust_pending; 1006 }; 1007 1008 1009 /* Passed on init */ 1010 enum vram_type { 1011 VIDEO_MEMORY_TYPE_GDDR5 = 2, 1012 VIDEO_MEMORY_TYPE_DDR3 = 3, 1013 VIDEO_MEMORY_TYPE_DDR4 = 4, 1014 VIDEO_MEMORY_TYPE_HBM = 5, 1015 VIDEO_MEMORY_TYPE_GDDR6 = 6, 1016 }; 1017 1018 enum dwb_cnv_out_bpc { 1019 DWB_CNV_OUT_BPC_8BPC = 0, 1020 DWB_CNV_OUT_BPC_10BPC = 1, 1021 }; 1022 1023 enum dwb_output_depth { 1024 DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0, 1025 DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1, 1026 }; 1027 1028 enum dwb_capture_rate { 1029 dwb_capture_rate_0 = 0, /* Every frame is captured. */ 1030 dwb_capture_rate_1 = 1, /* Every other frame is captured. */ 1031 dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */ 1032 dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */ 1033 }; 1034 1035 enum dwb_scaler_mode { 1036 dwb_scaler_mode_bypass444 = 0, 1037 dwb_scaler_mode_rgb444 = 1, 1038 dwb_scaler_mode_yuv444 = 2, 1039 dwb_scaler_mode_yuv420 = 3 1040 }; 1041 1042 enum dwb_subsample_position { 1043 DWB_INTERSTITIAL_SUBSAMPLING = 0, 1044 DWB_COSITED_SUBSAMPLING = 1 1045 }; 1046 1047 enum dwb_stereo_eye_select { 1048 DWB_STEREO_EYE_LEFT = 1, /* Capture left eye only */ 1049 DWB_STEREO_EYE_RIGHT = 2, /* Capture right eye only */ 1050 }; 1051 1052 enum dwb_stereo_type { 1053 DWB_STEREO_TYPE_FRAME_PACKING = 0, /* Frame packing */ 1054 DWB_STEREO_TYPE_FRAME_SEQUENTIAL = 3, /* Frame sequential */ 1055 }; 1056 1057 enum dwb_out_format { 1058 DWB_OUT_FORMAT_32BPP_ARGB = 0, 1059 DWB_OUT_FORMAT_32BPP_RGBA = 1, 1060 DWB_OUT_FORMAT_64BPP_ARGB = 2, 1061 DWB_OUT_FORMAT_64BPP_RGBA = 3 1062 }; 1063 1064 enum dwb_out_denorm { 1065 DWB_OUT_DENORM_10BPC = 0, 1066 DWB_OUT_DENORM_8BPC = 1, 1067 DWB_OUT_DENORM_BYPASS = 2 1068 }; 1069 1070 enum cm_gamut_remap_select { 1071 CM_GAMUT_REMAP_MODE_BYPASS = 0, 1072 CM_GAMUT_REMAP_MODE_RAMA_COEFF, 1073 CM_GAMUT_REMAP_MODE_RAMB_COEFF, 1074 CM_GAMUT_REMAP_MODE_RESERVED 1075 }; 1076 1077 enum cm_gamut_coef_format { 1078 CM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0, 1079 CM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 1 1080 }; 1081 1082 enum mpcc_gamut_remap_mode_select { 1083 MPCC_GAMUT_REMAP_MODE_SELECT_0 = 0, 1084 MPCC_GAMUT_REMAP_MODE_SELECT_1, 1085 MPCC_GAMUT_REMAP_MODE_SELECT_2 1086 }; 1087 1088 enum mpcc_gamut_remap_id { 1089 MPCC_OGAM_GAMUT_REMAP, 1090 MPCC_MCM_FIRST_GAMUT_REMAP, 1091 MPCC_MCM_SECOND_GAMUT_REMAP 1092 }; 1093 1094 enum cursor_matrix_mode { 1095 CUR_MATRIX_BYPASS = 0, 1096 CUR_MATRIX_SET_A, 1097 CUR_MATRIX_SET_B 1098 }; 1099 1100 struct mcif_warmup_params { 1101 union large_integer start_address; 1102 unsigned int address_increment; 1103 unsigned int region_size; 1104 unsigned int p_vmid; 1105 }; 1106 1107 #define MCIF_BUF_COUNT 4 1108 1109 struct mcif_buf_params { 1110 unsigned long long luma_address[MCIF_BUF_COUNT]; 1111 unsigned long long chroma_address[MCIF_BUF_COUNT]; 1112 unsigned int luma_pitch; 1113 unsigned int chroma_pitch; 1114 unsigned int warmup_pitch; 1115 unsigned int swlock; 1116 unsigned int p_vmid; 1117 }; 1118 1119 1120 #define MAX_TG_COLOR_VALUE 0x3FF 1121 struct tg_color { 1122 /* Maximum 10 bits color value */ 1123 uint16_t color_r_cr; 1124 uint16_t color_g_y; 1125 uint16_t color_b_cb; 1126 }; 1127 1128 enum symclk_state { 1129 SYMCLK_OFF_TX_OFF, 1130 SYMCLK_ON_TX_ON, 1131 SYMCLK_ON_TX_OFF, 1132 }; 1133 1134 struct phy_state { 1135 struct { 1136 uint8_t otg : 1; 1137 uint8_t reserved : 7; 1138 } symclk_ref_cnts; 1139 enum symclk_state symclk_state; 1140 }; 1141 1142 #endif /* DC_HW_TYPES_H */ 1143 1144