1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * GS101 SoC 4 * 5 * Copyright 2019-2023 Google LLC 6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org> 7 */ 8 9#include <dt-bindings/clock/google,gs101.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/soc/samsung,exynos-usi.h> 13 14/ { 15 compatible = "google,gs101"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_gpio_alive; 23 pinctrl1 = &pinctrl_far_alive; 24 pinctrl2 = &pinctrl_gsacore; 25 pinctrl3 = &pinctrl_gsactrl; 26 pinctrl4 = &pinctrl_peric0; 27 pinctrl5 = &pinctrl_peric1; 28 pinctrl6 = &pinctrl_hsi1; 29 pinctrl7 = &pinctrl_hsi2; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu-map { 37 cluster0 { 38 core0 { 39 cpu = <&cpu0>; 40 }; 41 core1 { 42 cpu = <&cpu1>; 43 }; 44 core2 { 45 cpu = <&cpu2>; 46 }; 47 core3 { 48 cpu = <&cpu3>; 49 }; 50 }; 51 52 cluster1 { 53 core0 { 54 cpu = <&cpu4>; 55 }; 56 core1 { 57 cpu = <&cpu5>; 58 }; 59 }; 60 61 cluster2 { 62 core0 { 63 cpu = <&cpu6>; 64 }; 65 core1 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0000>; 75 enable-method = "psci"; 76 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 77 capacity-dmips-mhz = <250>; 78 dynamic-power-coefficient = <70>; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a55"; 84 reg = <0x0100>; 85 enable-method = "psci"; 86 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 87 capacity-dmips-mhz = <250>; 88 dynamic-power-coefficient = <70>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0200>; 95 enable-method = "psci"; 96 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 97 capacity-dmips-mhz = <250>; 98 dynamic-power-coefficient = <70>; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x0300>; 105 enable-method = "psci"; 106 cpu-idle-states = <&ANANKE_CPU_SLEEP>; 107 capacity-dmips-mhz = <250>; 108 dynamic-power-coefficient = <70>; 109 }; 110 111 cpu4: cpu@400 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a76"; 114 reg = <0x0400>; 115 enable-method = "psci"; 116 cpu-idle-states = <&ENYO_CPU_SLEEP>; 117 capacity-dmips-mhz = <620>; 118 dynamic-power-coefficient = <284>; 119 }; 120 121 cpu5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a76"; 124 reg = <0x0500>; 125 enable-method = "psci"; 126 cpu-idle-states = <&ENYO_CPU_SLEEP>; 127 capacity-dmips-mhz = <620>; 128 dynamic-power-coefficient = <284>; 129 }; 130 131 cpu6: cpu@600 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-x1"; 134 reg = <0x0600>; 135 enable-method = "psci"; 136 cpu-idle-states = <&HERA_CPU_SLEEP>; 137 capacity-dmips-mhz = <1024>; 138 dynamic-power-coefficient = <650>; 139 }; 140 141 cpu7: cpu@700 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-x1"; 144 reg = <0x0700>; 145 enable-method = "psci"; 146 cpu-idle-states = <&HERA_CPU_SLEEP>; 147 capacity-dmips-mhz = <1024>; 148 dynamic-power-coefficient = <650>; 149 }; 150 151 idle-states { 152 entry-method = "psci"; 153 154 ANANKE_CPU_SLEEP: cpu-ananke-sleep { 155 idle-state-name = "c2"; 156 compatible = "arm,idle-state"; 157 arm,psci-suspend-param = <0x0010000>; 158 local-timer-stop; 159 entry-latency-us = <70>; 160 exit-latency-us = <160>; 161 min-residency-us = <2000>; 162 }; 163 164 ENYO_CPU_SLEEP: cpu-enyo-sleep { 165 idle-state-name = "c2"; 166 compatible = "arm,idle-state"; 167 arm,psci-suspend-param = <0x0010000>; 168 local-timer-stop; 169 entry-latency-us = <150>; 170 exit-latency-us = <190>; 171 min-residency-us = <2500>; 172 }; 173 174 HERA_CPU_SLEEP: cpu-hera-sleep { 175 idle-state-name = "c2"; 176 compatible = "arm,idle-state"; 177 arm,psci-suspend-param = <0x0010000>; 178 local-timer-stop; 179 entry-latency-us = <235>; 180 exit-latency-us = <220>; 181 min-residency-us = <3500>; 182 }; 183 }; 184 }; 185 186 /* ect node is required to be present by bootloader */ 187 ect { 188 }; 189 190 ext_24_5m: clock-1 { 191 compatible = "fixed-clock"; 192 #clock-cells = <0>; 193 clock-output-names = "oscclk"; 194 }; 195 196 ext_200m: clock-2 { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 clock-output-names = "ext-200m"; 200 }; 201 202 pmu-0 { 203 compatible = "arm,cortex-a55-pmu"; 204 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 205 }; 206 207 pmu-1 { 208 compatible = "arm,cortex-a76-pmu"; 209 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 210 }; 211 212 pmu-2 { 213 compatible = "arm,cortex-x1-pmu"; 214 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>; 215 }; 216 217 pmu-3 { 218 compatible = "arm,dsu-pmu"; 219 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 220 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 221 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>; 222 }; 223 224 psci { 225 compatible = "arm,psci-1.0"; 226 method = "smc"; 227 }; 228 229 reserved_memory: reserved-memory { 230 #address-cells = <2>; 231 #size-cells = <1>; 232 ranges; 233 234 gsa_reserved_protected: gsa@90200000 { 235 reg = <0x0 0x90200000 0x400000>; 236 no-map; 237 }; 238 239 tpu_fw_reserved: tpu-fw@93000000 { 240 reg = <0x0 0x93000000 0x1000000>; 241 no-map; 242 }; 243 244 aoc_reserve: aoc@94000000 { 245 reg = <0x0 0x94000000 0x03000000>; 246 no-map; 247 }; 248 249 abl_reserved: abl@f8800000 { 250 reg = <0x0 0xf8800000 0x02000000>; 251 no-map; 252 }; 253 254 dss_log_reserved: dss-log-reserved@fd3f0000 { 255 reg = <0x0 0xfd3f0000 0x0000e000>; 256 no-map; 257 }; 258 259 debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 { 260 reg = <0x0 0xfd3fe000 0x00001000>; 261 no-map; 262 }; 263 264 bldr_log_reserved: bldr-log-reserved@fd800000 { 265 reg = <0x0 0xfd800000 0x00100000>; 266 no-map; 267 }; 268 269 bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 { 270 reg = <0x0 0xfd900000 0x00002000>; 271 no-map; 272 }; 273 }; 274 275 soc: soc@0 { 276 compatible = "simple-bus"; 277 #address-cells = <1>; 278 #size-cells = <1>; 279 ranges = <0x0 0x0 0x0 0x40000000>; 280 281 cmu_misc: clock-controller@10010000 { 282 compatible = "google,gs101-cmu-misc"; 283 reg = <0x10010000 0x8000>; 284 #clock-cells = <1>; 285 clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, 286 <&cmu_top CLK_DOUT_CMU_MISC_SSS>; 287 clock-names = "bus", "sss"; 288 }; 289 290 timer@10050000 { 291 compatible = "google,gs101-mct", 292 "samsung,exynos4210-mct"; 293 reg = <0x10050000 0x800>; 294 clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>; 295 clock-names = "fin_pll", "mct"; 296 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>, 297 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>, 298 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>, 299 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>, 300 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>, 301 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>, 302 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>, 303 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>, 304 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>, 305 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>, 306 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>, 307 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>; 308 }; 309 310 watchdog_cl0: watchdog@10060000 { 311 compatible = "google,gs101-wdt"; 312 reg = <0x10060000 0x100>; 313 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>, 314 <&ext_24_5m>; 315 clock-names = "watchdog", "watchdog_src"; 316 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>; 317 samsung,syscon-phandle = <&pmu_system_controller>; 318 samsung,cluster-index = <0>; 319 status = "disabled"; 320 }; 321 322 watchdog_cl1: watchdog@10070000 { 323 compatible = "google,gs101-wdt"; 324 reg = <0x10070000 0x100>; 325 clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>, 326 <&ext_24_5m>; 327 clock-names = "watchdog", "watchdog_src"; 328 interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>; 329 samsung,syscon-phandle = <&pmu_system_controller>; 330 samsung,cluster-index = <1>; 331 status = "disabled"; 332 }; 333 334 gic: interrupt-controller@10400000 { 335 compatible = "arm,gic-v3"; 336 #interrupt-cells = <4>; 337 interrupt-controller; 338 reg = <0x10400000 0x10000>, /* GICD */ 339 <0x10440000 0x100000>;/* GICR * 8 */ 340 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 341 342 ppi-partitions { 343 ppi_cluster0: interrupt-partition-0 { 344 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 345 }; 346 347 ppi_cluster1: interrupt-partition-1 { 348 affinity = <&cpu4 &cpu5>; 349 }; 350 351 ppi_cluster2: interrupt-partition-2 { 352 affinity = <&cpu6 &cpu7>; 353 }; 354 }; 355 }; 356 357 cmu_peric0: clock-controller@10800000 { 358 compatible = "google,gs101-cmu-peric0"; 359 reg = <0x10800000 0x4000>; 360 #clock-cells = <1>; 361 clocks = <&ext_24_5m>, 362 <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, 363 <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; 364 clock-names = "oscclk", "bus", "ip"; 365 }; 366 367 sysreg_peric0: syscon@10820000 { 368 compatible = "google,gs101-peric0-sysreg", "syscon"; 369 reg = <0x10820000 0x10000>; 370 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; 371 }; 372 373 pinctrl_peric0: pinctrl@10840000 { 374 compatible = "google,gs101-pinctrl"; 375 reg = <0x10840000 0x00001000>; 376 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>; 377 clock-names = "pclk"; 378 interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>; 379 }; 380 381 usi1: usi@109000c0 { 382 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 383 reg = <0x109000c0 0x20>; 384 ranges; 385 #address-cells = <1>; 386 #size-cells = <1>; 387 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 388 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 389 clock-names = "pclk", "ipclk"; 390 samsung,sysreg = <&sysreg_peric0 0x1000>; 391 status = "disabled"; 392 393 hsi2c_1: i2c@10900000 { 394 compatible = "google,gs101-hsi2c", 395 "samsung,exynosautov9-hsi2c"; 396 reg = <0x10900000 0xc0>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>, 400 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>; 401 clock-names = "hsi2c", "hsi2c_pclk"; 402 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 403 pinctrl-0 = <&hsi2c1_bus>; 404 pinctrl-names = "default"; 405 status = "disabled"; 406 }; 407 408 serial_1: serial@10900000 { 409 compatible = "google,gs101-uart"; 410 reg = <0x10900000 0xc0>; 411 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 412 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 413 clock-names = "uart", "clk_uart_baud0"; 414 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 415 pinctrl-0 = <&uart1_bus_single>; 416 pinctrl-names = "default"; 417 samsung,uart-fifosize = <64>; 418 status = "disabled"; 419 }; 420 421 spi_1: spi@10900000 { 422 compatible = "google,gs101-spi"; 423 reg = <0x10900000 0x30>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, 427 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; 428 clock-names = "spi", "spi_busclk0"; 429 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 430 pinctrl-0 = <&spi1_bus>; 431 pinctrl-names = "default"; 432 status = "disabled"; 433 }; 434 }; 435 436 usi2: usi@109100c0 { 437 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 438 reg = <0x109100c0 0x20>; 439 ranges; 440 #address-cells = <1>; 441 #size-cells = <1>; 442 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 443 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 444 clock-names = "pclk", "ipclk"; 445 samsung,sysreg = <&sysreg_peric0 0x1004>; 446 status = "disabled"; 447 448 hsi2c_2: i2c@10910000 { 449 compatible = "google,gs101-hsi2c", 450 "samsung,exynosautov9-hsi2c"; 451 reg = <0x10910000 0xc0>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>, 455 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>; 456 clock-names = "hsi2c", "hsi2c_pclk"; 457 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 458 pinctrl-0 = <&hsi2c2_bus>; 459 pinctrl-names = "default"; 460 status = "disabled"; 461 }; 462 463 serial_2: serial@10910000 { 464 compatible = "google,gs101-uart"; 465 reg = <0x10910000 0xc0>; 466 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 467 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 468 clock-names = "uart", "clk_uart_baud0"; 469 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 470 pinctrl-0 = <&uart2_bus_single>; 471 pinctrl-names = "default"; 472 samsung,uart-fifosize = <64>; 473 status = "disabled"; 474 }; 475 476 spi_2: spi@10910000 { 477 compatible = "google,gs101-spi"; 478 reg = <0x10910000 0x30>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, 482 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; 483 clock-names = "spi", "spi_busclk0"; 484 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 485 pinctrl-0 = <&spi2_bus>; 486 pinctrl-names = "default"; 487 status = "disabled"; 488 }; 489 }; 490 491 usi3: usi@109200c0 { 492 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 493 reg = <0x109200c0 0x20>; 494 ranges; 495 #address-cells = <1>; 496 #size-cells = <1>; 497 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 498 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 499 clock-names = "pclk", "ipclk"; 500 samsung,sysreg = <&sysreg_peric0 0x1008>; 501 status = "disabled"; 502 503 hsi2c_3: i2c@10920000 { 504 compatible = "google,gs101-hsi2c", 505 "samsung,exynosautov9-hsi2c"; 506 reg = <0x10920000 0xc0>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>, 510 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>; 511 clock-names = "hsi2c", "hsi2c_pclk"; 512 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 513 pinctrl-0 = <&hsi2c3_bus>; 514 pinctrl-names = "default"; 515 status = "disabled"; 516 }; 517 518 serial_3: serial@10920000 { 519 compatible = "google,gs101-uart"; 520 reg = <0x10920000 0xc0>; 521 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 522 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 523 clock-names = "uart", "clk_uart_baud0"; 524 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 525 pinctrl-0 = <&uart3_bus_single>; 526 pinctrl-names = "default"; 527 samsung,uart-fifosize = <64>; 528 status = "disabled"; 529 }; 530 531 spi_3: spi@10920000 { 532 compatible = "google,gs101-spi"; 533 reg = <0x10920000 0x30>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, 537 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; 538 clock-names = "spi", "spi_busclk0"; 539 interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>; 540 pinctrl-0 = <&spi3_bus>; 541 pinctrl-names = "default"; 542 status = "disabled"; 543 }; 544 }; 545 546 usi4: usi@109300c0 { 547 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 548 reg = <0x109300c0 0x20>; 549 ranges; 550 #address-cells = <1>; 551 #size-cells = <1>; 552 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 553 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 554 clock-names = "pclk", "ipclk"; 555 samsung,sysreg = <&sysreg_peric0 0x100c>; 556 status = "disabled"; 557 558 hsi2c_4: i2c@10930000 { 559 compatible = "google,gs101-hsi2c", 560 "samsung,exynosautov9-hsi2c"; 561 reg = <0x10930000 0xc0>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>, 565 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>; 566 clock-names = "hsi2c", "hsi2c_pclk"; 567 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 568 pinctrl-0 = <&hsi2c4_bus>; 569 pinctrl-names = "default"; 570 status = "disabled"; 571 }; 572 573 serial_4: serial@10930000 { 574 compatible = "google,gs101-uart"; 575 reg = <0x10930000 0xc0>; 576 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 577 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 578 clock-names = "uart", "clk_uart_baud0"; 579 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 580 pinctrl-0 = <&uart4_bus_single>; 581 pinctrl-names = "default"; 582 samsung,uart-fifosize = <64>; 583 status = "disabled"; 584 }; 585 586 spi_4: spi@10930000 { 587 compatible = "google,gs101-spi"; 588 reg = <0x10930000 0x30>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, 592 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; 593 clock-names = "spi", "spi_busclk0"; 594 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 595 pinctrl-0 = <&spi4_bus>; 596 pinctrl-names = "default"; 597 status = "disabled"; 598 }; 599 }; 600 601 usi5: usi@109400c0 { 602 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 603 reg = <0x109400c0 0x20>; 604 ranges; 605 #address-cells = <1>; 606 #size-cells = <1>; 607 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 608 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 609 clock-names = "pclk", "ipclk"; 610 samsung,sysreg = <&sysreg_peric0 0x1010>; 611 status = "disabled"; 612 613 hsi2c_5: i2c@10940000 { 614 compatible = "google,gs101-hsi2c", 615 "samsung,exynosautov9-hsi2c"; 616 reg = <0x10940000 0xc0>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>, 620 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>; 621 clock-names = "hsi2c", "hsi2c_pclk"; 622 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 623 pinctrl-0 = <&hsi2c5_bus>; 624 pinctrl-names = "default"; 625 status = "disabled"; 626 }; 627 628 serial_5: serial@10940000 { 629 compatible = "google,gs101-uart"; 630 reg = <0x10940000 0xc0>; 631 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 632 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 633 clock-names = "uart", "clk_uart_baud0"; 634 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 635 pinctrl-0 = <&uart5_bus_single>; 636 pinctrl-names = "default"; 637 samsung,uart-fifosize = <64>; 638 status = "disabled"; 639 }; 640 641 spi_5: spi@10940000 { 642 compatible = "google,gs101-spi"; 643 reg = <0x10940000 0x30>; 644 #address-cells = <1>; 645 #size-cells = <0>; 646 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, 647 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; 648 clock-names = "spi", "spi_busclk0"; 649 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 650 pinctrl-0 = <&spi5_bus>; 651 pinctrl-names = "default"; 652 status = "disabled"; 653 }; 654 }; 655 656 usi6: usi@109500c0 { 657 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 658 reg = <0x109500c0 0x20>; 659 ranges; 660 #address-cells = <1>; 661 #size-cells = <1>; 662 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 663 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 664 clock-names = "pclk", "ipclk"; 665 samsung,sysreg = <&sysreg_peric0 0x1014>; 666 status = "disabled"; 667 668 hsi2c_6: i2c@10950000 { 669 compatible = "google,gs101-hsi2c", 670 "samsung,exynosautov9-hsi2c"; 671 reg = <0x10950000 0xc0>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>, 675 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>; 676 clock-names = "hsi2c", "hsi2c_pclk"; 677 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 678 pinctrl-0 = <&hsi2c6_bus>; 679 pinctrl-names = "default"; 680 status = "disabled"; 681 }; 682 683 serial_6: serial@10950000 { 684 compatible = "google,gs101-uart"; 685 reg = <0x10950000 0xc0>; 686 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 687 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 688 clock-names = "uart", "clk_uart_baud0"; 689 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 690 pinctrl-0 = <&uart6_bus_single>; 691 pinctrl-names = "default"; 692 samsung,uart-fifosize = <64>; 693 status = "disabled"; 694 }; 695 696 spi_6: spi@10950000 { 697 compatible = "google,gs101-spi"; 698 reg = <0x10950000 0x30>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, 702 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; 703 clock-names = "spi", "spi_busclk0"; 704 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 705 pinctrl-0 = <&spi6_bus>; 706 pinctrl-names = "default"; 707 status = "disabled"; 708 }; 709 }; 710 711 usi7: usi@109600c0 { 712 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 713 reg = <0x109600c0 0x20>; 714 ranges; 715 #address-cells = <1>; 716 #size-cells = <1>; 717 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 718 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 719 clock-names = "pclk", "ipclk"; 720 samsung,sysreg = <&sysreg_peric0 0x1018>; 721 status = "disabled"; 722 723 hsi2c_7: i2c@10960000 { 724 compatible = "google,gs101-hsi2c", 725 "samsung,exynosautov9-hsi2c"; 726 reg = <0x10960000 0xc0>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>, 730 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>; 731 clock-names = "hsi2c", "hsi2c_pclk"; 732 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 733 pinctrl-0 = <&hsi2c7_bus>; 734 pinctrl-names = "default"; 735 status = "disabled"; 736 }; 737 738 serial_7: serial@10960000 { 739 compatible = "google,gs101-uart"; 740 reg = <0x10960000 0xc0>; 741 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 742 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 743 clock-names = "uart", "clk_uart_baud0"; 744 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 745 pinctrl-0 = <&uart7_bus_single>; 746 pinctrl-names = "default"; 747 samsung,uart-fifosize = <64>; 748 status = "disabled"; 749 }; 750 751 spi_7: spi@10960000 { 752 compatible = "google,gs101-spi"; 753 reg = <0x10960000 0x30>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, 757 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; 758 clock-names = "spi", "spi_busclk0"; 759 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 760 pinctrl-0 = <&spi7_bus>; 761 pinctrl-names = "default"; 762 status = "disabled"; 763 }; 764 }; 765 766 usi8: usi@109700c0 { 767 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 768 reg = <0x109700c0 0x20>; 769 ranges; 770 #address-cells = <1>; 771 #size-cells = <1>; 772 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 773 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 774 clock-names = "pclk", "ipclk"; 775 samsung,sysreg = <&sysreg_peric0 0x101c>; 776 status = "disabled"; 777 778 hsi2c_8: i2c@10970000 { 779 compatible = "google,gs101-hsi2c", 780 "samsung,exynosautov9-hsi2c"; 781 reg = <0x10970000 0xc0>; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, 785 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; 786 clock-names = "hsi2c", "hsi2c_pclk"; 787 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 788 pinctrl-0 = <&hsi2c8_bus>; 789 pinctrl-names = "default"; 790 status = "disabled"; 791 }; 792 793 serial_8: serial@10970000 { 794 compatible = "google,gs101-uart"; 795 reg = <0x10970000 0xc0>; 796 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 797 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 798 clock-names = "uart", "clk_uart_baud0"; 799 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 800 pinctrl-0 = <&uart8_bus_single>; 801 pinctrl-names = "default"; 802 samsung,uart-fifosize = <64>; 803 status = "disabled"; 804 }; 805 806 spi_8: spi@10970000 { 807 compatible = "google,gs101-spi"; 808 reg = <0x10970000 0x30>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, 812 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; 813 clock-names = "spi", "spi_busclk0"; 814 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 815 pinctrl-0 = <&spi8_bus>; 816 pinctrl-names = "default"; 817 status = "disabled"; 818 }; 819 }; 820 821 usi_uart: usi@10a000c0 { 822 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 823 reg = <0x10a000c0 0x20>; 824 ranges; 825 #address-cells = <1>; 826 #size-cells = <1>; 827 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 828 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 829 clock-names = "pclk", "ipclk"; 830 samsung,sysreg = <&sysreg_peric0 0x1020>; 831 samsung,mode = <USI_V2_UART>; 832 status = "disabled"; 833 834 serial_0: serial@10a00000 { 835 compatible = "google,gs101-uart"; 836 reg = <0x10a00000 0xc0>; 837 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, 838 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; 839 clock-names = "uart", "clk_uart_baud0"; 840 interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>; 841 pinctrl-0 = <&uart0_bus>; 842 pinctrl-names = "default"; 843 samsung,uart-fifosize = <256>; 844 status = "disabled"; 845 }; 846 }; 847 848 usi14: usi@10a200c0 { 849 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 850 reg = <0x10a200c0 0x20>; 851 ranges; 852 #address-cells = <1>; 853 #size-cells = <1>; 854 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 855 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 856 clock-names = "pclk", "ipclk"; 857 samsung,sysreg = <&sysreg_peric0 0x1028>; 858 status = "disabled"; 859 860 hsi2c_14: i2c@10a20000 { 861 compatible = "google,gs101-hsi2c", 862 "samsung,exynosautov9-hsi2c"; 863 reg = <0x10a20000 0xc0>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>, 867 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>; 868 clock-names = "hsi2c", "hsi2c_pclk"; 869 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 870 pinctrl-0 = <&hsi2c14_bus>; 871 pinctrl-names = "default"; 872 status = "disabled"; 873 }; 874 875 serial_14: serial@10a20000 { 876 compatible = "google,gs101-uart"; 877 reg = <0x10a20000 0xc0>; 878 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 879 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 880 clock-names = "uart", "clk_uart_baud0"; 881 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 882 pinctrl-0 = <&uart14_bus_single>; 883 pinctrl-names = "default"; 884 samsung,uart-fifosize = <64>; 885 status = "disabled"; 886 }; 887 888 spi_14: spi@10a20000 { 889 compatible = "google,gs101-spi"; 890 reg = <0x10a20000 0x30>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, 894 <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; 895 clock-names = "spi", "spi_busclk0"; 896 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 897 pinctrl-0 = <&spi14_bus>; 898 pinctrl-names = "default"; 899 status = "disabled"; 900 }; 901 }; 902 903 cmu_peric1: clock-controller@10c00000 { 904 compatible = "google,gs101-cmu-peric1"; 905 reg = <0x10c00000 0x4000>; 906 #clock-cells = <1>; 907 clocks = <&ext_24_5m>, 908 <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, 909 <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; 910 clock-names = "oscclk", "bus", "ip"; 911 }; 912 913 sysreg_peric1: syscon@10c20000 { 914 compatible = "google,gs101-peric1-sysreg", "syscon"; 915 reg = <0x10c20000 0x10000>; 916 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; 917 }; 918 919 pinctrl_peric1: pinctrl@10c40000 { 920 compatible = "google,gs101-pinctrl"; 921 reg = <0x10c40000 0x00001000>; 922 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>; 923 clock-names = "pclk"; 924 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 925 }; 926 927 usi0: usi@10d100c0 { 928 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 929 reg = <0x10d100c0 0x20>; 930 ranges; 931 #address-cells = <1>; 932 #size-cells = <1>; 933 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 934 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 935 clock-names = "pclk", "ipclk"; 936 samsung,sysreg = <&sysreg_peric1 0x1000>; 937 status = "disabled"; 938 939 hsi2c_0: i2c@10d10000 { 940 compatible = "google,gs101-hsi2c", 941 "samsung,exynosautov9-hsi2c"; 942 reg = <0x10d10000 0xc0>; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>, 946 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>; 947 clock-names = "hsi2c", "hsi2c_pclk"; 948 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 949 pinctrl-0 = <&hsi2c0_bus>; 950 pinctrl-names = "default"; 951 status = "disabled"; 952 }; 953 954 serial_usi0: serial@10d10000 { 955 compatible = "google,gs101-uart"; 956 reg = <0x10d10000 0xc0>; 957 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 958 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 959 clock-names = "uart", "clk_uart_baud0"; 960 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 961 pinctrl-0 = <&uart0_bus_single>; 962 pinctrl-names = "default"; 963 samsung,uart-fifosize = <64>; 964 status = "disabled"; 965 }; 966 967 spi_0: spi@10d10000 { 968 compatible = "google,gs101-spi"; 969 reg = <0x10d10000 0x30>; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, 973 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; 974 clock-names = "spi", "spi_busclk0"; 975 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>; 976 pinctrl-0 = <&spi0_bus>; 977 pinctrl-names = "default"; 978 status = "disabled"; 979 }; 980 }; 981 982 usi9: usi@10d200c0 { 983 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 984 reg = <0x10d200c0 0x20>; 985 ranges; 986 #address-cells = <1>; 987 #size-cells = <1>; 988 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 989 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 990 clock-names = "pclk", "ipclk"; 991 samsung,sysreg = <&sysreg_peric1 0x1004>; 992 status = "disabled"; 993 994 hsi2c_9: i2c@10d20000 { 995 compatible = "google,gs101-hsi2c", 996 "samsung,exynosautov9-hsi2c"; 997 reg = <0x10d20000 0xc0>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>, 1001 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>; 1002 clock-names = "hsi2c", "hsi2c_pclk"; 1003 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1004 pinctrl-0 = <&hsi2c9_bus>; 1005 pinctrl-names = "default"; 1006 status = "disabled"; 1007 }; 1008 1009 serial_9: serial@10d20000 { 1010 compatible = "google,gs101-uart"; 1011 reg = <0x10d20000 0xc0>; 1012 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1013 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1014 clock-names = "uart", "clk_uart_baud0"; 1015 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1016 pinctrl-0 = <&uart9_bus_single>; 1017 pinctrl-names = "default"; 1018 samsung,uart-fifosize = <64>; 1019 status = "disabled"; 1020 }; 1021 1022 spi_9: spi@10d20000 { 1023 compatible = "google,gs101-spi"; 1024 reg = <0x10d20000 0x30>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, 1028 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; 1029 clock-names = "spi", "spi_busclk0"; 1030 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>; 1031 pinctrl-0 = <&spi9_bus>; 1032 pinctrl-names = "default"; 1033 status = "disabled"; 1034 }; 1035 }; 1036 1037 usi10: usi@10d300c0 { 1038 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1039 reg = <0x10d300c0 0x20>; 1040 ranges; 1041 #address-cells = <1>; 1042 #size-cells = <1>; 1043 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1044 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1045 clock-names = "pclk", "ipclk"; 1046 samsung,sysreg = <&sysreg_peric1 0x1008>; 1047 status = "disabled"; 1048 1049 hsi2c_10: i2c@10d30000 { 1050 compatible = "google,gs101-hsi2c", 1051 "samsung,exynosautov9-hsi2c"; 1052 reg = <0x10d30000 0xc0>; 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>, 1056 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>; 1057 clock-names = "hsi2c", "hsi2c_pclk"; 1058 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1059 pinctrl-0 = <&hsi2c10_bus>; 1060 pinctrl-names = "default"; 1061 status = "disabled"; 1062 }; 1063 1064 serial_10: serial@10d30000 { 1065 compatible = "google,gs101-uart"; 1066 reg = <0x10d30000 0xc0>; 1067 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1068 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1069 clock-names = "uart", "clk_uart_baud0"; 1070 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1071 pinctrl-0 = <&uart10_bus_single>; 1072 pinctrl-names = "default"; 1073 samsung,uart-fifosize = <64>; 1074 status = "disabled"; 1075 }; 1076 1077 spi_10: spi@10d30000 { 1078 compatible = "google,gs101-spi"; 1079 reg = <0x10d30000 0x30>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, 1083 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; 1084 clock-names = "spi", "spi_busclk0"; 1085 interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>; 1086 pinctrl-0 = <&spi10_bus>; 1087 pinctrl-names = "default"; 1088 status = "disabled"; 1089 }; 1090 }; 1091 1092 usi11: usi@10d400c0 { 1093 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1094 reg = <0x10d400c0 0x20>; 1095 ranges; 1096 #address-cells = <1>; 1097 #size-cells = <1>; 1098 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1099 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1100 clock-names = "pclk", "ipclk"; 1101 samsung,sysreg = <&sysreg_peric1 0x100c>; 1102 status = "disabled"; 1103 1104 hsi2c_11: i2c@10d40000 { 1105 compatible = "google,gs101-hsi2c", 1106 "samsung,exynosautov9-hsi2c"; 1107 reg = <0x10d40000 0xc0>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>, 1111 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>; 1112 clock-names = "hsi2c", "hsi2c_pclk"; 1113 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1114 pinctrl-0 = <&hsi2c11_bus>; 1115 pinctrl-names = "default"; 1116 status = "disabled"; 1117 }; 1118 1119 serial_11: serial@10d40000 { 1120 compatible = "google,gs101-uart"; 1121 reg = <0x10d40000 0xc0>; 1122 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1123 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1124 clock-names = "uart", "clk_uart_baud0"; 1125 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1126 pinctrl-0 = <&uart11_bus_single>; 1127 pinctrl-names = "default"; 1128 samsung,uart-fifosize = <64>; 1129 status = "disabled"; 1130 }; 1131 1132 spi_11: spi@10d40000 { 1133 compatible = "google,gs101-spi"; 1134 reg = <0x10d40000 0x30>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, 1138 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; 1139 clock-names = "spi", "spi_busclk0"; 1140 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 1141 pinctrl-0 = <&spi11_bus>; 1142 pinctrl-names = "default"; 1143 status = "disabled"; 1144 }; 1145 }; 1146 1147 usi12: usi@10d500c0 { 1148 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1149 reg = <0x10d500c0 0x20>; 1150 ranges; 1151 #address-cells = <1>; 1152 #size-cells = <1>; 1153 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1154 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1155 clock-names = "pclk", "ipclk"; 1156 samsung,sysreg = <&sysreg_peric1 0x1010>; 1157 status = "disabled"; 1158 1159 hsi2c_12: i2c@10d50000 { 1160 compatible = "google,gs101-hsi2c", 1161 "samsung,exynosautov9-hsi2c"; 1162 reg = <0x10d50000 0xc0>; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, 1166 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; 1167 clock-names = "hsi2c", "hsi2c_pclk"; 1168 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1169 pinctrl-0 = <&hsi2c12_bus>; 1170 pinctrl-names = "default"; 1171 status = "disabled"; 1172 }; 1173 1174 serial_12: serial@10d50000 { 1175 compatible = "google,gs101-uart"; 1176 reg = <0x10d50000 0xc0>; 1177 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1178 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1179 clock-names = "uart", "clk_uart_baud0"; 1180 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1181 pinctrl-0 = <&uart12_bus_single>; 1182 pinctrl-names = "default"; 1183 samsung,uart-fifosize = <64>; 1184 status = "disabled"; 1185 }; 1186 1187 spi_12: spi@10d50000 { 1188 compatible = "google,gs101-spi"; 1189 reg = <0x10d50000 0x30>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, 1193 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; 1194 clock-names = "spi", "spi_busclk0"; 1195 interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>; 1196 pinctrl-0 = <&spi12_bus>; 1197 pinctrl-names = "default"; 1198 status = "disabled"; 1199 }; 1200 }; 1201 1202 usi13: usi@10d600c0 { 1203 compatible = "google,gs101-usi", "samsung,exynos850-usi"; 1204 reg = <0x10d600c0 0x20>; 1205 ranges; 1206 #address-cells = <1>; 1207 #size-cells = <1>; 1208 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1209 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1210 clock-names = "pclk", "ipclk"; 1211 samsung,sysreg = <&sysreg_peric1 0x1014>; 1212 status = "disabled"; 1213 1214 hsi2c_13: i2c@10d60000 { 1215 compatible = "google,gs101-hsi2c", 1216 "samsung,exynosautov9-hsi2c"; 1217 reg = <0x10d60000 0xc0>; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>, 1221 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>; 1222 clock-names = "hsi2c", "hsi2c_pclk"; 1223 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1224 pinctrl-0 = <&hsi2c13_bus>; 1225 pinctrl-names = "default"; 1226 status = "disabled"; 1227 }; 1228 1229 serial_13: serial@10d60000 { 1230 compatible = "google,gs101-uart"; 1231 reg = <0x10d60000 0xc0>; 1232 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1233 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1234 clock-names = "uart", "clk_uart_baud0"; 1235 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1236 pinctrl-0 = <&uart13_bus_single>; 1237 pinctrl-names = "default"; 1238 samsung,uart-fifosize = <64>; 1239 status = "disabled"; 1240 }; 1241 1242 spi_13: spi@10d60000 { 1243 compatible = "google,gs101-spi"; 1244 reg = <0x10d60000 0x30>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, 1248 <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; 1249 clock-names = "spi", "spi_busclk0"; 1250 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 1251 pinctrl-0 = <&spi13_bus>; 1252 pinctrl-names = "default"; 1253 status = "disabled"; 1254 }; 1255 }; 1256 1257 cmu_hsi0: clock-controller@11000000 { 1258 compatible = "google,gs101-cmu-hsi0"; 1259 reg = <0x11000000 0x4000>; 1260 #clock-cells = <1>; 1261 1262 clocks = <&ext_24_5m>, 1263 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, 1264 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>, 1265 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, 1266 <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; 1267 clock-names = "oscclk", "bus", "dpgtc", "usb31drd", 1268 "usbdpdbg"; 1269 }; 1270 1271 usbdrd31_phy: phy@11100000 { 1272 compatible = "google,gs101-usb31drd-phy"; 1273 reg = <0x11100000 0x0100>, 1274 <0x110f0000 0x0800>, 1275 <0x110e0000 0x2800>; 1276 reg-names = "phy", "pcs", "pma"; 1277 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, 1278 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>, 1279 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>, 1280 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, 1281 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; 1282 clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; 1283 #phy-cells = <1>; 1284 samsung,pmu-syscon = <&pmu_system_controller>; 1285 status = "disabled"; 1286 }; 1287 1288 usbdrd31: usb@11110000 { 1289 compatible = "google,gs101-dwusb3"; 1290 ranges = <0x0 0x11110000 0x10000>; 1291 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, 1292 <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, 1293 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, 1294 <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; 1295 clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; 1296 #address-cells = <1>; 1297 #size-cells = <1>; 1298 status = "disabled"; 1299 1300 usbdrd31_dwc3: usb@0 { 1301 compatible = "snps,dwc3"; 1302 reg = <0x0 0x10000>; 1303 clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; 1304 clock-names = "ref"; 1305 interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; 1306 phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; 1307 phy-names = "usb2-phy", "usb3-phy"; 1308 status = "disabled"; 1309 }; 1310 }; 1311 1312 pinctrl_hsi1: pinctrl@11840000 { 1313 compatible = "google,gs101-pinctrl"; 1314 reg = <0x11840000 0x00001000>; 1315 /* TODO: update once support for this CMU exists */ 1316 clocks = <0>; 1317 clock-names = "pclk"; 1318 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>; 1319 }; 1320 1321 cmu_hsi2: clock-controller@14400000 { 1322 compatible = "google,gs101-cmu-hsi2"; 1323 reg = <0x14400000 0x4000>; 1324 #clock-cells = <1>; 1325 clocks = <&ext_24_5m>, 1326 <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, 1327 <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, 1328 <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, 1329 <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; 1330 clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; 1331 }; 1332 1333 sysreg_hsi2: syscon@14420000 { 1334 compatible = "google,gs101-hsi2-sysreg", "syscon"; 1335 reg = <0x14420000 0x10000>; 1336 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1337 }; 1338 1339 pinctrl_hsi2: pinctrl@14440000 { 1340 compatible = "google,gs101-pinctrl"; 1341 reg = <0x14440000 0x00001000>; 1342 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>; 1343 clock-names = "pclk"; 1344 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 1345 }; 1346 1347 ufs_0: ufs@14700000 { 1348 compatible = "google,gs101-ufs"; 1349 reg = <0x14700000 0x200>, 1350 <0x14701100 0x200>, 1351 <0x14780000 0xa000>, 1352 <0x14600000 0x100>; 1353 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1354 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1355 clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, 1356 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, 1357 <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, 1358 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, 1359 <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, 1360 <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; 1361 clock-names = "core_clk", "sclk_unipro_main", "fmp", 1362 "aclk", "pclk", "sysreg"; 1363 dma-coherent; 1364 freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; 1365 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1366 pinctrl-names = "default"; 1367 phys = <&ufs_0_phy>; 1368 phy-names = "ufs-phy"; 1369 samsung,sysreg = <&sysreg_hsi2 0x710>; 1370 status = "disabled"; 1371 }; 1372 1373 ufs_0_phy: phy@14704000 { 1374 compatible = "google,gs101-ufs-phy"; 1375 reg = <0x14704000 0x3000>; 1376 reg-names = "phy-pma"; 1377 samsung,pmu-syscon = <&pmu_system_controller>; 1378 #phy-cells = <0>; 1379 clocks = <&ext_24_5m>; 1380 clock-names = "ref_clk"; 1381 status = "disabled"; 1382 }; 1383 1384 cmu_apm: clock-controller@17400000 { 1385 compatible = "google,gs101-cmu-apm"; 1386 reg = <0x17400000 0x8000>; 1387 #clock-cells = <1>; 1388 1389 clocks = <&ext_24_5m>; 1390 clock-names = "oscclk"; 1391 }; 1392 1393 sysreg_apm: syscon@174204e0 { 1394 compatible = "google,gs101-apm-sysreg", "syscon"; 1395 reg = <0x174204e0 0x1000>; 1396 }; 1397 1398 pmu_system_controller: system-controller@17460000 { 1399 compatible = "google,gs101-pmu", "syscon"; 1400 reg = <0x17460000 0x10000>; 1401 1402 poweroff: syscon-poweroff { 1403 compatible = "syscon-poweroff"; 1404 regmap = <&pmu_system_controller>; 1405 offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */ 1406 mask = <0x100>; /* reset value */ 1407 }; 1408 1409 reboot: syscon-reboot { 1410 compatible = "syscon-reboot"; 1411 regmap = <&pmu_system_controller>; 1412 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 1413 mask = <0x2>; /* SWRESET_SYSTEM */ 1414 value = <0x2>; /* reset value */ 1415 }; 1416 }; 1417 1418 pinctrl_gpio_alive: pinctrl@174d0000 { 1419 compatible = "google,gs101-pinctrl"; 1420 reg = <0x174d0000 0x00001000>; 1421 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>; 1422 clock-names = "pclk"; 1423 1424 wakeup-interrupt-controller { 1425 compatible = "google,gs101-wakeup-eint", 1426 "samsung,exynos850-wakeup-eint", 1427 "samsung,exynos7-wakeup-eint"; 1428 }; 1429 }; 1430 1431 pinctrl_far_alive: pinctrl@174e0000 { 1432 compatible = "google,gs101-pinctrl"; 1433 reg = <0x174e0000 0x00001000>; 1434 clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>; 1435 clock-names = "pclk"; 1436 1437 wakeup-interrupt-controller { 1438 compatible = "google,gs101-wakeup-eint", 1439 "samsung,exynos850-wakeup-eint", 1440 "samsung,exynos7-wakeup-eint"; 1441 }; 1442 }; 1443 1444 pinctrl_gsactrl: pinctrl@17940000 { 1445 compatible = "google,gs101-pinctrl"; 1446 reg = <0x17940000 0x00001000>; 1447 /* TODO: update once support for this CMU exists */ 1448 clocks = <0>; 1449 clock-names = "pclk"; 1450 }; 1451 1452 pinctrl_gsacore: pinctrl@17a80000 { 1453 compatible = "google,gs101-pinctrl"; 1454 reg = <0x17a80000 0x00001000>; 1455 /* TODO: update once support for this CMU exists */ 1456 clocks = <0>; 1457 clock-names = "pclk"; 1458 status = "disabled"; 1459 }; 1460 1461 cmu_top: clock-controller@1e080000 { 1462 compatible = "google,gs101-cmu-top"; 1463 reg = <0x1e080000 0x8000>; 1464 #clock-cells = <1>; 1465 1466 clocks = <&ext_24_5m>; 1467 clock-names = "oscclk"; 1468 }; 1469 }; 1470 1471 timer { 1472 compatible = "arm,armv8-timer"; 1473 interrupts = 1474 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1475 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1476 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>, 1477 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>; 1478 }; 1479}; 1480 1481#include "gs101-pinctrl.dtsi" 1482